riscv/rocket-chip
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Remove spurious vec consts

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This commit is contained in:
Henry Cook 2014-09-24 22:17:28 -07:00
parent 3e256439c9
commit b55c38cdc7
2 changed files with 1 additions and 27 deletions
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25
rocket/src/main/scala/consts.scala
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@ -61,28 +61,3 @@ trait ScalarOpConstants {
val RA = UInt(1, 5)
}
trait VectorOpConstants {
val VEC_X = Bits("b??", 2).toUInt
val VEC_FN_N = UInt(0, 2)
val VEC_VL = UInt(1, 2)
val VEC_CFG = UInt(2, 2)
val VEC_CFGVL = UInt(3, 2)
val VCMD_I = UInt(0, 3)
val VCMD_F = UInt(1, 3)
val VCMD_TX = UInt(2, 3)
val VCMD_TF = UInt(3, 3)
val VCMD_MX = UInt(4, 3)
val VCMD_MF = UInt(5, 3)
val VCMD_A = UInt(6, 3)
val VCMD_X = UInt(0, 3)
val VIMM_VLEN = UInt(0, 1)
val VIMM_ALU = UInt(1, 1)
val VIMM_X = UInt(0, 1)
val VIMM2_RS2 = UInt(0, 1)
val VIMM2_ALU = UInt(1, 1)
val VIMM2_X = UInt(0, 1)
}

3
rocket/src/main/scala/package.scala
View File

@ -1,8 +1,7 @@
// See LICENSE for license details.
package object rocket extends
rocket.constants.ScalarOpConstants with
rocket.constants.VectorOpConstants
rocket.constants.ScalarOpConstants
{
val START_ADDR = 0x2000
}