riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao f34b0b0447 make sure L2 tracker doesn't read data array again if data buffer already filled 2016-07-29 16:47:31 -07:00
Howard Mao 2891eb879a add MergedPutRegression to uncover merged put after release bug in L2 2016-07-29 16:42:28 -07:00
Howard Mao 064020bdd7 make sure Memtest generators write different data to each address 2016-07-29 14:22:46 -07:00
Howard Mao 5a3beca097 add RepeatedGetRegression to uncover L2 merged get miss bug 2016-07-28 19:58:47 -07:00
Howard Mao cb86aaa46b fix trace generator addresses 2016-07-28 17:56:14 -07:00
Howard Mao bd5972503f move groundtest/scripts to top-level scripts/ 2016-07-28 11:36:55 -07:00
Howard Mao 478f494626 Merge remote-tracking branch 'groundtest/master' into mono-repo 2016-07-28 11:28:06 -07:00
Howard Mao a5b88d0bdc Merge remote-tracking branch 'junctions/master' into mono-repo 2016-07-28 11:27:47 -07:00
Howard Mao 373fd427dc Merge remote-tracking branch 'rocket/master' into mono-repo 2016-07-28 11:27:29 -07:00
Howard Mao ce242b8f3f Merge remote-tracking branch 'uncore/master' into mono-repo 2016-07-28 11:23:31 -07:00
Howard Mao aefba04fb3 get rid of submodules in preparation for merging 2016-07-28 11:21:08 -07:00
Howard Mao 6de2a3e3b1 get rid of fpga-zynq submodule 2016-07-28 11:07:47 -07:00
Howard Mao fe51a35fa9 a few more submodule bumps 2016-07-28 09:25:59 -07:00
Howard Mao bf35f980a6 make sure PTE cache is power of 2 in size to satisfy PseudoLRU requirement 2016-07-27 18:40:38 -07:00
Howard Mao fbcc7317cf make sure PseudoLRU is given power of 2 ways 2016-07-27 18:39:33 -07:00
Howard Mao 15d1aa9346 make sure TrackerAllocationIO addr_block has correct direction set 2016-07-27 16:47:22 -07:00
Howard Mao 9c89290efc fix LRSC issue (fixes issue #86) 2016-07-26 22:25:04 -07:00
Howard Mao 0bd7ef1278 re-enable SCs inflight with other requests 2016-07-26 22:21:41 -07:00
Howard Mao df07771fa0 add uncached noise generator to TraceGen 2016-07-26 22:21:10 -07:00
Howard Mao dcfcac9530 fix LRSC issue (RocketChip issue #86) 
It was possible that the result of a store-conditional could get lost if it
did not depend on the result of the corresponding load-reserved.

This was because the MSHR does not update the client state based on the
secondary requests. So the LR would acquire the line in clientExcusiveClean,
but then we would fail to update the metadata array to change the state
to clientExclusiveDirty.

The solution is to track whether a secondary acquire would cause the
line to be dirty. If so, use M_XWR instead of the primary command to
generate the update coherence state.
 2016-07-26 18:41:52 -07:00
Howard Mao ecd1af326c fix L2 deadlock bug and add more advanced trace generator 2016-07-26 12:43:08 -07:00
Howard Mao 82bbbf908d Fix L2 Writeback deadlock issue 
The deadlock condition occurs when the acquire tracker attempts to
request a writeback while the writeback unit is still busy and a
voluntary release for the block to be written back is coming in.

The voluntary release cannot be accepted because it conflicts with the
acquire tracker. The acquire tracker can't merge the voluntary release
because it is waiting to send the writeback. The writeback can't
progress because the release it is waiting on is behind the voluntary
release.

The solution to this is to break the atomicity guarantee between the
acquire tracker and the writeback unit. This allows the voluntary
release tracker to take the voluntary release before the writeback unit
accepts the conflicting request. This causes a potential race condition
for the metadata array. The solution to this is to have the writeback
unit re-read the metadata after accepting a request.
 2016-07-26 12:31:08 -07:00
Howard Mao 1063d90993 make sure L1 and L2 agree on coherence policy 2016-07-25 12:20:49 -07:00
Howard Mao 6a5b2d7f59 fix assembly tests for configurations without VMU and/or user mode 2016-07-22 17:21:57 -07:00
Howard Mao 51edd19e85 add U bit to misa register 2016-07-22 14:22:59 -07:00
Howard Mao 75347eed56 some fixes and cleanup to stateless bridge 2016-07-21 19:51:26 -07:00
Howard Mao 9168f35971 clean up the requirements in StatelessBridge 
* No need to check that release ID bits and acquire ID bits the same
 * Check that inner and outer coherence policies match
 2016-07-21 19:41:56 -07:00
Howard Mao 12067a3b8d make sure outer probe and finish lines are disconnected 2016-07-21 15:15:44 -07:00
Howard Mao c38dff0855 add some more warnings about the StatelessBridge 2016-07-21 15:07:10 -07:00
Howard Mao 0a1cd64786 fix number of builtin Acquire types 2016-07-21 13:45:20 -07:00
Howard Mao ffe17cbb2b bump uncore for L2 bugfix 2016-07-21 12:35:38 -07:00
Howard Mao 20df74d138 generate more L1 voluntary releases in TraceGen 2016-07-21 12:33:55 -07:00
Howard Mao 86e31be820 fix lockup from back to back releases with data 2016-07-21 12:06:58 -07:00
Howard Mao 24ef4e6dea make sure to use AND not OR for combining finished signals 2016-07-21 12:05:11 -07:00
Howard Mao d77d0ddc5d rename CacheTest.scala to CacheFillTest.scala 2016-07-20 20:37:45 -07:00
Howard Mao d56362f04c add configuration checks for TraceGen 2016-07-20 10:37:10 -07:00
Howard Mao 959630630a give LCG an inc signal and add object constructors 2016-07-20 10:36:28 -07:00
Howard Mao b013925ab0 make sure ReleaseRegression starts only on io.start 2016-07-19 15:42:45 -07:00
Howard Mao 577c73667b use getSimpleName to dump out test names 2016-07-19 14:42:58 -07:00
Howard Mao 1dac2930eb fix bug in WriteMaskedPutBlockRegression 2016-07-19 14:42:23 -07:00
Howard Mao 19b44ec95b Bug fixes in SimpleHellaCacheIF and L2 agents 
* SimpleHellaCacheIF now properly handles both the non-blocking data
   cache and blocking data cache.
 * SimpleHellaCacheIF maintains ordering of replayed requests
 * L2 VoluntaryReleaseTracker sends voluntary release grant properly
 * Coherence protocols now downgrade for probeCopy
 2016-07-19 09:35:13 -07:00
Howard Mao bc39d52655 changes to multi-transaction timer 2016-07-18 18:26:18 -07:00
Howard Mao 9eeb1112d4 fix Bufferless irel_vs_iacq_conflict signal 2016-07-18 17:38:20 -07:00
Howard Mao e5cccc0526 don't update xact_vol_irel if not a voluntary irel 2016-07-18 17:05:23 -07:00
Howard Mao 2723b2f515 fix issues in SimpleHellaCacheIF and document the changes 2016-07-18 17:02:47 -07:00
Howard Mao 40a146f625 HellaCacheArbiter passes through if n == 1 2016-07-18 17:01:29 -07:00
Howard Mao 39a1ecbf3c switch groundtest to merged master 2016-07-18 09:34:27 -07:00
Howard Mao 359252fdc1 fix a width bug 2016-07-18 09:33:17 -07:00
Howard Mao 6fc4236782 add atomic and prefetch drivers 2016-07-18 09:33:17 -07:00
Howard Mao 2ec736ed67 reorder some code in the Nasti unit tests 2016-07-18 09:33:17 -07:00
Howard Mao 3ea299b062 make unit test debug output more meaningful 2016-07-18 09:33:17 -07:00
Howard Mao def740406c fix a few Driver bugs 2016-07-18 09:33:17 -07:00
Howard Mao 8278a73e83 group unit tests by their tested interface 2016-07-18 09:33:17 -07:00
Howard Mao 9c0fffdd1c start constructing composable tilelink unit test drivers 2016-07-18 09:33:17 -07:00
Howard Mao c92732dcaa rename MemoryTestDriver to NastiDriver 2016-07-18 09:33:16 -07:00
Howard Mao c906e6edde some renaming 2016-07-18 09:33:16 -07:00
Howard Mao 1c2bf6e938 make list of unit tests a a parameter 2016-07-18 09:33:16 -07:00
Howard Mao 69eebaf362 factor out unit tests into separate package 2016-07-18 09:33:16 -07:00
Howard Mao e08ec42bc0 refactor groundtest unittests into separate package 2016-07-16 23:19:55 -07:00
Howard Mao 59d700bf66 fix combinational loop in NASTI -> HASTI converter 2016-07-15 18:45:37 -07:00
Howard Mao 897e6ccf8a fix Hasti and Smi converters 2016-07-15 15:39:00 -07:00
Howard Mao 84098db81f add a TileLinkTestRAM 2016-07-15 11:03:26 -07:00
Howard Mao 66b9c5ad05 fix up cloneType calls in clock crossers 2016-07-13 14:31:19 -07:00
Howard Mao 18ea58c85f remove unnecessary CAMs from converters 2016-07-13 12:42:50 -07:00
Howard Mao b122a54c32 don't allow more outer IDs than inner IDs 2016-07-13 12:42:28 -07:00
Howard Mao 37fd11870c fix up ReorderQueue CAM 2016-07-13 12:11:43 -07:00
Howard Mao de1e25f3d1 reduce usage of CAMs in converters 2016-07-13 11:20:50 -07:00
Howard Mao c0dc09b3a1 don't use CAM in ReorderQueue if not necessary 2016-07-13 11:08:15 -07:00
Howard Mao f3775df04d fix the condition under which comparator error signal is set 2016-07-12 18:37:13 -07:00
Howard Mao 4c79215fde add a script for checking comparator trace 2016-07-12 14:42:04 -07:00
Howard Mao 88dc0b983a make sure Comparator logs correctly when prefetching off 2016-07-12 14:36:46 -07:00
Howard Mao 676a536706 fix bugs from adding ComparatorSource backpressure 2016-07-12 13:50:34 -07:00
Howard Mao d435bb4185 reduce hardware usage of Comparator to allow it to synthesize 2016-07-12 10:54:18 -07:00
Howard Mao 90bcd3dbdc make sure DirectGroundTest testers given correct TL settings 2016-07-11 18:11:01 -07:00
Howard Mao 8f0fa11ce4 optionally export detailed status information in DirectGroundTest 2016-07-11 18:11:00 -07:00
Howard Mao b64998ec05 make sure dramsim reads and writes occur in the order they are received 2016-07-11 18:11:00 -07:00
Howard Mao cb2a18b533 allow direct instatiation of arbitrary non-caching groundtests 2016-07-11 18:11:00 -07:00
Howard Mao f03ffb32a0 add top that directly tests the TL -> AXI converters 2016-07-11 18:11:00 -07:00
Howard Mao b47f8fbc41 don't use splat and bug out if too many address map entries 2016-07-11 18:10:42 -07:00
Howard Mao 18967642de export more detailed status data from GroundTest 2016-07-11 16:41:55 -07:00
Howard Mao e194677087 fix comparator PutBlock data generation and debug output 2016-07-11 12:15:37 -07:00
Howard Mao 5a3d6a1583 NastiTest should cycle through write ids 2016-07-08 17:55:02 -07:00
Howard Mao 9ec55ebb91 don't add io:ext region to address map if no external MMIO 2016-07-08 15:29:35 -07:00
Howard Mao 35547aa428 allow NastiConverterTest and Memtest to run simultaneously 2016-07-08 13:40:52 -07:00
Howard Mao d80c2f480f make NastiConverterTest act as generator and share blocks 2016-07-08 13:39:46 -07:00
Howard Mao 358668699f refactoring groundtest configuration 2016-07-08 11:40:16 -07:00
Howard Mao 850fa092a4 refactor how groundtests are configured 2016-07-08 11:40:01 -07:00
Howard Mao eeac405ef8 get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache 2016-07-08 09:33:07 -07:00
Howard Mao 8aa73915a1 put locking arbiter back into converter 2016-07-08 09:31:33 -07:00
Howard Mao a50ba39ea7 Revert "add buffering and locking to TL -> Nasti converter" 
This reverts commit 2109a48e18719383942d535ff4c1d0a859dcc424.

Conflicts:
	src/main/scala/converters/Nasti.scala
 2016-07-08 09:31:33 -07:00
Howard Mao f7b392306e make sure SimpleHellaCacheIF can work with blocking DCache 2016-07-07 18:59:23 -07:00
Howard Mao f62c74b82a allow groundtest to use non-blocking DCache 2016-07-07 18:59:09 -07:00
Howard Mao 67871654dd start NastiConverterTest higher up in memory 2016-07-07 14:35:04 -07:00
Howard Mao 16a6b11081 fix bug in AXI -> TL converter 2016-07-07 14:34:24 -07:00
Howard Mao 7cc64011fb simplify amo_mask generation 2016-07-07 12:14:45 -07:00
Howard Mao 1c5e7be75b make sure Nasti write channel id is set correctly 2016-07-07 12:14:02 -07:00
Howard Mao 6055482513 make sure write channel id is actually set 2016-07-07 12:12:39 -07:00
Howard Mao 8ccc50a8f0 fix IdMapper and TL -> NASTI converter 2016-07-07 10:16:44 -07:00
Howard Mao 8c13e78ab5 add buffering and locking to TL -> AXI converter 2016-07-06 16:57:09 -07:00
Howard Mao e27cb5f885 fix voluntary release issue in L2 cache 2016-07-06 16:57:01 -07:00