riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

some renaming

Browse Source
This commit is contained in:
Howard Mao 2016-07-14 13:41:59 -07:00
parent 1c2bf6e938
commit c906e6edde
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
groundtest/src/main/scala/unittests/TileLinkToSmiConverterTest.scala → groundtest/src/main/scala/unittests/SmiConverterTest.scala
View File

@ -8,7 +8,7 @@ import uncore.converters._
import uncore.constants._
import cde.Parameters
class TileLinkToSmiConverterTestDriver(implicit p: Parameters) extends Module {
class SmiConverterTestDriver(implicit p: Parameters) extends Module {
val io = new Bundle {
val mem = new ClientUncachedTileLinkIO
val start = Bool(INPUT)
@ -74,12 +74,12 @@ class TileLinkToSmiConverterTestDriver(implicit p: Parameters) extends Module {
io.finished := (state === s_finished)
}
class TileLinkToSmiConverterTest(implicit p: Parameters) extends UnitTest {
class SmiConverterTest(implicit p: Parameters) extends UnitTest {
val outermostParams = p.alterPartial({ case TLId => "Outermost" })
val smimem = Module(new SmiMem(32, 64))
val conv = Module(new SmiIOTileLinkIOConverter(32, 6)(outermostParams))
val driver = Module(new TileLinkToSmiConverterTestDriver()(outermostParams))
val driver = Module(new SmiConverterTestDriver()(outermostParams))
conv.io.tl <> driver.io.mem
smimem.io <> conv.io.smi