group unit tests by their tested interface
This commit is contained in:
Howard Mao
parent
9c0fffdd1c
commit
8278a73e83
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@ -1,127 +0,0 @@
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package groundtest.unittests
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import Chisel._
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import junctions._
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import junctions.NastiConstants._
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import cde.Parameters
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class AtosConverterTestFrontend(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = new NastiIO
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val finished = Bool(OUTPUT)
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}
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val n_words = 4
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val test_data = Vec.tabulate(n_words) { i => UInt(i * 48) }
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val (s_idle :: s_waddr :: s_wdata :: s_wresp ::
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s_raddr :: s_rresp :: s_done :: Nil) = Enum(Bits(), 7)
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val state = Reg(init = s_idle)
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when (state === s_idle) { state := s_waddr }
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when (io.nasti.aw.fire()) { state := s_wdata }
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when (io.nasti.w.fire() && io.nasti.w.bits.last) { state := s_wresp }
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when (io.nasti.b.fire()) { state := s_raddr }
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when (io.nasti.ar.fire()) { state := s_rresp }
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when (io.nasti.r.fire() && io.nasti.r.bits.last) { state := s_done }
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val (w_count, w_last) = Counter(io.nasti.w.fire(), n_words)
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io.nasti.aw.valid := (state === s_waddr)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt(log2Up(nastiXDataBits / 8)),
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len = UInt(n_words - 1))
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io.nasti.w.valid := (state === s_wdata)
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io.nasti.w.bits := NastiWriteDataChannel(
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data = test_data(w_count),
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last = w_count === UInt(n_words - 1))
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io.nasti.ar.valid := (state === s_raddr)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt(log2Up(nastiXDataBits / 8)),
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len = UInt(n_words - 1))
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io.nasti.b.ready := (state === s_wresp)
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io.nasti.r.ready := (state === s_rresp)
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io.finished := (state === s_done)
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val (r_count, r_last) = Counter(io.nasti.r.fire(), n_words)
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assert(!io.nasti.r.valid || io.nasti.r.bits.data === test_data(r_count),
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"AtosConverterTest: returned data doesn't match expected")
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}
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class AtosConverterTestBackend(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = (new NastiIO).flip
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val finished = Bool(OUTPUT)
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}
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val (s_waddr :: s_wdata :: s_wresp ::
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s_raddr :: s_rresp :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_waddr)
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val n_words = 4
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val test_data = Reg(Vec(n_words, UInt(width = nastiXDataBits)))
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val req_id = Reg(UInt(width = nastiXIdBits))
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val (w_count, w_last) = Counter(io.nasti.w.fire(), n_words)
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val (r_count, r_last) = Counter(io.nasti.r.fire(), n_words)
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when (io.nasti.aw.fire()) {
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req_id := io.nasti.aw.bits.id
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state := s_wdata
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}
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when (io.nasti.w.fire()) {
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test_data(w_count) := io.nasti.w.bits.data
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when (io.nasti.w.bits.last) { state := s_wresp }
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}
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when (io.nasti.b.fire()) { state := s_raddr }
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when (io.nasti.ar.fire()) {
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req_id := io.nasti.ar.bits.id
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state := s_rresp
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}
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when (io.nasti.r.fire() && io.nasti.r.bits.last) { state := s_done }
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io.nasti.aw.ready := (state === s_waddr)
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io.nasti.w.ready := (state === s_wdata)
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io.nasti.ar.ready := (state === s_raddr)
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io.nasti.b.valid := (state === s_wresp)
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io.nasti.b.bits := NastiWriteResponseChannel(id = req_id)
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io.nasti.r.valid := (state === s_rresp)
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io.nasti.r.bits := NastiReadDataChannel(
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id = req_id,
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data = test_data(r_count),
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last = r_last)
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io.finished := (state === s_done)
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}
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class AtosConverterTest(implicit p: Parameters) extends UnitTest {
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val frontend = Module(new AtosConverterTestFrontend)
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val backend = Module(new AtosConverterTestBackend)
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val serdes = Module(new AtosSerdes(8))
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val desser = Module(new AtosDesser(8))
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val client_conv = Module(new AtosClientConverter)
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val manager_conv = Module(new AtosManagerConverter)
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client_conv.io.nasti <> frontend.io.nasti
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serdes.io.wide <> client_conv.io.atos
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desser.io.narrow <> serdes.io.narrow
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manager_conv.io.atos <> desser.io.wide
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backend.io.nasti <> manager_conv.io.nasti
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io.finished := frontend.io.finished && backend.io.finished
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}
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@ -1,82 +0,0 @@
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package groundtest.unittests
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import Chisel._
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import uncore.tilelink._
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import uncore.devices._
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import cde.Parameters
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class BRAMSlaveDriver(implicit val p: Parameters) extends Module
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with HasTileLinkParameters {
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val io = new Bundle {
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val mem = new ClientUncachedTileLinkIO
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val start = Bool(INPUT)
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val finished = Bool(OUTPUT)
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}
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val (s_idle :: s_pf_req :: s_pf_stall :: s_pf_resp ::
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s_put_req :: s_put_stall :: s_put_resp ::
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s_get_req :: s_get_stall :: s_get_resp ::
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s_done :: Nil) = Enum(Bits(), 11)
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val state = Reg(init = s_idle)
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val pf_acquire = PutPrefetch(
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client_xact_id = UInt(0),
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addr_block = UInt(0))
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val (put_beat, put_done) = Counter(
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state === s_put_req && io.mem.acquire.ready, tlDataBeats)
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val put_data = Fill(tlDataBits / tlBeatAddrBits, put_beat)
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val put_acquire = PutBlock(
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client_xact_id = UInt(0),
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addr_block = UInt(0),
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addr_beat = put_beat,
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data = put_data)
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val get_acquire = GetBlock(
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client_xact_id = UInt(0),
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addr_block = UInt(0))
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val (get_beat, get_done) = Counter(
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state === s_get_resp && io.mem.grant.valid, tlDataBeats)
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val get_data = Fill(tlDataBits / tlBeatAddrBits, get_beat)
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val (stall_cnt, stall_done) = Counter(
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state === s_pf_stall || state === s_put_stall || state === s_get_stall, 4)
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io.mem.acquire.valid := (state === s_pf_req) || (state === s_put_req) || (state === s_get_req)
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io.mem.acquire.bits := MuxLookup(state, get_acquire, Seq(
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s_pf_req -> pf_acquire,
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s_put_req -> put_acquire))
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io.mem.grant.ready := (state === s_pf_resp) || (state === s_put_resp) || (state === s_get_resp)
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when (state === s_idle && io.start) { state := s_pf_req }
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when (state === s_pf_req && io.mem.acquire.ready) { state := s_pf_stall }
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when (state === s_pf_stall && stall_done) { state := s_pf_resp }
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when (state === s_pf_resp && io.mem.grant.valid) { state := s_put_req }
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when (state === s_put_req && io.mem.acquire.ready) { state := s_put_stall }
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when (state === s_put_stall && stall_done) { state := s_put_req }
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when (put_done) { state := s_put_resp }
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when (state === s_put_resp && io.mem.grant.valid) { state := s_get_req }
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when (state === s_get_req && io.mem.acquire.ready) { state := s_get_stall }
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when (state === s_get_stall && stall_done) { state := s_get_resp }
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when (state === s_get_resp && io.mem.grant.valid) { state := s_get_stall }
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when (get_done) { state := s_done }
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io.finished := (state === s_done)
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assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() ||
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io.mem.grant.bits.data === get_data,
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"BRAMSlaveTest: data doesn't match")
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}
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class BRAMSlaveTest(implicit val p: Parameters) extends UnitTest
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with HasTileLinkParameters {
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val driver = Module(new BRAMSlaveDriver)
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val bram = Module(new BRAMSlave(tlDataBeats))
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driver.io.start := io.start
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io.finished := driver.io.finished
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bram.io <> driver.io.mem
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}
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@ -2,11 +2,58 @@ package groundtest.unittests
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import Chisel._
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import junctions._
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import uncore.devices._
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import uncore.tilelink._
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import junctions.NastiConstants._
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import groundtest.common._
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import cde.Parameters
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class AtosConverterTestBackend(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = (new NastiIO).flip
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val finished = Bool(OUTPUT)
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}
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val (s_waddr :: s_wdata :: s_wresp ::
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s_raddr :: s_rresp :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_waddr)
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val n_words = 4
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val test_data = Reg(Vec(n_words, UInt(width = nastiXDataBits)))
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val req_id = Reg(UInt(width = nastiXIdBits))
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val (w_count, w_last) = Counter(io.nasti.w.fire(), n_words)
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val (r_count, r_last) = Counter(io.nasti.r.fire(), n_words)
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when (io.nasti.aw.fire()) {
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req_id := io.nasti.aw.bits.id
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state := s_wdata
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}
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when (io.nasti.w.fire()) {
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test_data(w_count) := io.nasti.w.bits.data
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when (io.nasti.w.bits.last) { state := s_wresp }
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}
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when (io.nasti.b.fire()) { state := s_raddr }
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when (io.nasti.ar.fire()) {
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req_id := io.nasti.ar.bits.id
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state := s_rresp
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}
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when (io.nasti.r.fire() && io.nasti.r.bits.last) { state := s_done }
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io.nasti.aw.ready := (state === s_waddr)
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io.nasti.w.ready := (state === s_wdata)
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io.nasti.ar.ready := (state === s_raddr)
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io.nasti.b.valid := (state === s_wresp)
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io.nasti.b.bits := NastiWriteResponseChannel(id = req_id)
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io.nasti.r.valid := (state === s_rresp)
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io.nasti.r.bits := NastiReadDataChannel(
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id = req_id,
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data = test_data(r_count),
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last = r_last)
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io.finished := (state === s_done)
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}
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class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int)
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(implicit p: Parameters) extends NastiModule {
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val io = new Bundle {
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@ -98,39 +145,24 @@ class HastiTest(implicit p: Parameters) extends UnitTest {
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driver.io.start := io.start
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}
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class ROMSlaveTest(implicit p: Parameters) extends UnitTest {
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val romdata = Seq(
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BigInt("01234567deadbeef", 16),
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BigInt("ab32fee8d00dfeed", 16))
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val rombytes = romdata.map(_.toByteArray.reverse).flatten
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val rom = Module(new ROMSlave(rombytes))
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val driver = Module(new DriverSet(
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(driverParams: Parameters) => {
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implicit val p = driverParams
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Seq(
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Module(new GetMultiWidthDriver),
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Module(new GetSweepDriver(romdata)),
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Module(new GetBlockSweepDriver(romdata)))
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}))
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rom.io <> driver.io.mem
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driver.io.start := io.start
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io.finished := driver.io.finished
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class AtosConverterTest(implicit val p: Parameters) extends UnitTest
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with HasNastiParameters {
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val frontend = Module(new NastiDriver(nastiXDataBits, 4, 1))
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val backend = Module(new AtosConverterTestBackend)
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val serdes = Module(new AtosSerdes(8))
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val desser = Module(new AtosDesser(8))
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val client_conv = Module(new AtosClientConverter)
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val manager_conv = Module(new AtosManagerConverter)
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client_conv.io.nasti <> frontend.io.nasti
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serdes.io.wide <> client_conv.io.atos
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desser.io.narrow <> serdes.io.narrow
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manager_conv.io.atos <> desser.io.wide
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backend.io.nasti <> manager_conv.io.nasti
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io.finished := frontend.io.finished && backend.io.finished
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}
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class TileLinkRAMTest(implicit val p: Parameters)
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extends UnitTest with HasTileLinkParameters {
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val depth = 2 * tlDataBeats
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val ram = Module(new TileLinkTestRAM(depth))
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val driver = Module(new DriverSet(
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(driverParams: Parameters) => {
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implicit val p = driverParams
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Seq(
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Module(new PutSweepDriver(depth)),
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Module(new PutMaskDriver),
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Module(new PutBlockSweepDriver(depth / tlDataBeats)))
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}))
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ram.io <> driver.io.mem
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driver.io.start := io.start
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io.finished := driver.io.finished
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}
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@ -1,89 +0,0 @@
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package groundtest.unittests
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import Chisel._
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import junctions._
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import uncore.tilelink._
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import uncore.converters._
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import uncore.constants._
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import cde.Parameters
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class SmiConverterTestDriver(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val mem = new ClientUncachedTileLinkIO
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val start = Bool(INPUT)
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val finished = Bool(OUTPUT)
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}
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val nChecks = 32
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val count = Reg(init = UInt(0, log2Up(nChecks)))
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val addr = Cat(count, UInt(0, 2))
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val data = Fill(4, count)
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val (s_idle :: s_wreq :: s_wresp :: s_rreq :: s_rresp ::
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s_finished :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_idle)
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when (state === s_idle && io.start) { state := s_wreq }
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when (state === s_wreq && io.mem.acquire.ready) { state := s_wresp }
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when (state === s_wresp && io.mem.grant.valid) {
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count := count + UInt(1)
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when (count === UInt(nChecks - 1)) {
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state := s_rreq
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} .otherwise {
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state := s_wreq
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}
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}
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when (state === s_rreq && io.mem.acquire.ready) { state := s_rresp }
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when (state === s_rresp && io.mem.grant.valid) {
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count := count + UInt(1)
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when (count === UInt(nChecks - 1)) {
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state := s_finished
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} .otherwise {
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state := s_rreq
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}
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}
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val blockOffsetBits = p(CacheBlockOffsetBits)
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val byteAddrBits = log2Up(p(TLKey(p(TLId))).writeMaskBits)
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io.mem.acquire.valid := (state === s_wreq) || (state === s_rreq)
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io.mem.acquire.bits := Mux(state === s_wreq,
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Put(
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client_xact_id = UInt(0),
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addr_block = addr >> UInt(blockOffsetBits),
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addr_beat = addr(blockOffsetBits - 1, byteAddrBits),
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data = Mux(count(0), data << UInt(32), data),
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wmask = Some(FillInterleaved(4, UIntToOH(count(0))))),
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Get(
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client_xact_id = UInt(0),
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addr_block = addr >> UInt(blockOffsetBits),
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addr_beat = addr(blockOffsetBits - 1, byteAddrBits),
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addr_byte = addr(byteAddrBits - 1, 0),
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operand_size = MT_W,
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alloc = Bool(false)))
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io.mem.grant.ready := (state === s_wresp) || (state === s_rresp)
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assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() ||
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Mux(count(0),
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io.mem.grant.bits.data(63, 32) === data,
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io.mem.grant.bits.data(31, 0) === data),
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"Test Driver got incorrect data")
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io.finished := (state === s_finished)
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}
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class SmiConverterTest(implicit p: Parameters) extends UnitTest {
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val outermostParams = p.alterPartial({ case TLId => "Outermost" })
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val smimem = Module(new SmiMem(32, 64))
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val conv = Module(new SmiIOTileLinkIOConverter(32, 6)(outermostParams))
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val driver = Module(new SmiConverterTestDriver()(outermostParams))
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conv.io.tl <> driver.io.mem
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smimem.io <> conv.io.smi
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driver.io.start := io.start
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io.finished := driver.io.finished
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}
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74
groundtest/src/main/scala/unittests/TileLink.scala
Normal file
74
groundtest/src/main/scala/unittests/TileLink.scala
Normal file
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@ -0,0 +1,74 @@
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package groundtest.unittests
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|
||||
import Chisel._
|
||||
import junctions._
|
||||
import uncore.devices._
|
||||
import uncore.tilelink._
|
||||
import uncore.converters._
|
||||
import groundtest.common._
|
||||
import cde.Parameters
|
||||
|
||||
class SmiConverterTest(implicit val p: Parameters) extends UnitTest
|
||||
with HasTileLinkParameters {
|
||||
val outermostParams = p.alterPartial({ case TLId => "Outermost" })
|
||||
|
||||
val smiWidth = 32
|
||||
val smiDepth = 64
|
||||
val tlDepth = (smiWidth * smiDepth) / tlDataBits
|
||||
|
||||
val smimem = Module(new SmiMem(smiWidth, smiDepth))
|
||||
val conv = Module(new SmiIOTileLinkIOConverter(
|
||||
smiWidth, log2Up(smiDepth))(outermostParams))
|
||||
val driver = Module(new DriverSet(
|
||||
(driverParams: Parameters) => {
|
||||
implicit val p = driverParams
|
||||
Seq(
|
||||
Module(new PutSweepDriver(tlDepth)),
|
||||
Module(new PutMaskDriver(smiWidth / 8)),
|
||||
Module(new PutBlockSweepDriver(tlDepth / tlDataBeats)))
|
||||
})(outermostParams))
|
||||
|
||||
conv.io.tl <> driver.io.mem
|
||||
smimem.io <> conv.io.smi
|
||||
driver.io.start := io.start
|
||||
io.finished := driver.io.finished
|
||||
}
|
||||
|
||||
class ROMSlaveTest(implicit p: Parameters) extends UnitTest {
|
||||
implicit val testName = "ROMSlaveTest"
|
||||
val romdata = Seq(
|
||||
BigInt("01234567deadbeef", 16),
|
||||
BigInt("ab32fee8d00dfeed", 16))
|
||||
val rombytes = romdata.map(_.toByteArray.reverse).flatten
|
||||
val rom = Module(new ROMSlave(rombytes))
|
||||
val driver = Module(new DriverSet(
|
||||
(driverParams: Parameters) => {
|
||||
implicit val p = driverParams
|
||||
Seq(
|
||||
Module(new GetMultiWidthDriver),
|
||||
Module(new GetSweepDriver(romdata)),
|
||||
Module(new GetBlockSweepDriver(romdata)))
|
||||
}))
|
||||
rom.io <> driver.io.mem
|
||||
driver.io.start := io.start
|
||||
io.finished := driver.io.finished
|
||||
}
|
||||
|
||||
class TileLinkRAMTest(implicit val p: Parameters)
|
||||
extends UnitTest with HasTileLinkParameters {
|
||||
|
||||
val depth = 2 * tlDataBeats
|
||||
val ram = Module(new TileLinkTestRAM(depth))
|
||||
val driver = Module(new DriverSet(
|
||||
(driverParams: Parameters) => {
|
||||
implicit val p = driverParams
|
||||
Seq(
|
||||
Module(new PutSweepDriver(depth)),
|
||||
Module(new PutMaskDriver),
|
||||
Module(new PutBlockSweepDriver(depth / tlDataBeats)))
|
||||
}))
|
||||
ram.io <> driver.io.mem
|
||||
driver.io.start := io.start
|
||||
io.finished := driver.io.finished
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user