riscv/rocket-chip
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make sure to use AND not OR for combining finished signals

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This commit is contained in:
Howard Mao 2016-07-21 12:05:11 -07:00
parent d77d0ddc5d
commit 24ef4e6dea
1 changed files with 1 additions and 1 deletions
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2
groundtest/src/main/scala/common/Util.scala
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@ -192,7 +192,7 @@ object ValidMux {
object DebugCombiner {
def apply(debugs: Seq[GroundTestStatus]): GroundTestStatus = {
val out = Wire(new GroundTestStatus)
out.finished := debugs.map(_.finished).reduce(_ || _)
out.finished := debugs.map(_.finished).reduce(_ && _)
out.timeout := ValidMux(debugs.map(_.timeout))
out.error := ValidMux(debugs.map(_.error))
out