riscv/rocket-chip
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generate more L1 voluntary releases in TraceGen

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This commit is contained in:
Howard Mao 2016-07-20 11:06:47 -07:00
parent 9ae23f18bd
commit 20df74d138
2 changed files with 15 additions and 4 deletions
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2
groundtest

@ -1 +1 @@
Subproject commit 2c3cb00867c1e78db4dc8360fd61745843abed95
Subproject commit 26f8823eaccadc4ad74ce9d4b73c6b388b53c21a

17
src/main/scala/TestConfigs.scala
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@ -179,17 +179,28 @@ class WithUnitTest extends Config(
})
class WithTraceGen extends Config(
(pname, site, here) => pname match {
topDefinitions = (pname, site, here) => pname match {
case GroundTestKey => Seq.fill(site(NTiles)) {
GroundTestTileSettings(cached = 1)
}
case BuildGroundTest =>
(p: Parameters) => Module(new GroundTestTraceGenerator()(p))
case GeneratorKey => GeneratorParameters(
maxRequests = 128,
maxRequests = 256,
startAddress = 0)
case AddressBag => List(0x8, 0x10, 0x108, 0x100008)
case AddressBag => {
val nSets = 16
val nWays = 1
val blockOffset = site(CacheBlockOffsetBits)
List.tabulate(2 * nWays) { i =>
Seq.tabulate(2) { j => (i * nSets + j * 8) << blockOffset }
}.flatten
}
case _ => throw new CDEMatchError
},
knobValues = {
case "L1D_SETS" => 16
case "L1D_WAYS" => 1
})
class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)