riscv/rocket-chip
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make sure dramsim reads and writes occur in the order they are received

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This commit is contained in:
Howard Mao
2016-07-11 12:16:24 -07:00
parent cb2a18b533
commit b64998ec05
2 changed files with 12 additions and 29 deletions
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19
csrc/mm_dramsim2.cc
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@@ -17,13 +17,12 @@ using namespace DRAMSim;
void mm_dramsim2_t::read_complete(unsigned id, uint64_t address, uint64_t clock_cycle)
{
auto req = rreq[address].front();
uint64_t start_addr = (address / word_size) * word_size;
for (int i = 0; i < req.len; i++) {
auto dat = read(start_addr + i * word_size);
rresp.push(mm_rresp_t(req.id, dat, (i == req.len - 1)));
}
rreq[address].pop();
mm_rresp_t resp;
do {
resp = rreq[address].front();
rresp.push(resp);
rreq[address].pop();
} while (!resp.last);
}
void mm_dramsim2_t::write_complete(unsigned id, uint64_t address, uint64_t clock_cycle)
@@ -85,7 +84,11 @@ void mm_dramsim2_t::tick(
bool b_fire = b_valid() && b_ready;
if (ar_fire) {
rreq[ar_addr].push(mm_req_t(ar_id, ar_len + 1, ar_addr));
uint64_t start_addr = (ar_addr / word_size) * word_size;
for (int i = 0; i <= ar_len; i++) {
auto dat = read(start_addr + i * word_size);
rreq[ar_addr].push(mm_rresp_t(ar_id, dat, (i == ar_len)));
}
mem->addTransaction(false, ar_addr);
}

22
csrc/mm_dramsim2.h
View File

@@ -9,26 +9,6 @@
#include <queue>
#include <stdint.h>
struct mm_req_t {
uint64_t id;
uint64_t len;
uint64_t addr;
mm_req_t(uint64_t id, uint64_t len, uint64_t addr)
{
this->id = id;
this->len = len;
this->addr = addr;
}
mm_req_t()
{
this->id = 0;
this->len = 0;
this->addr = 0;
}
};
class mm_dramsim2_t : public mm_t
{
public:
@@ -85,7 +65,7 @@ class mm_dramsim2_t : public mm_t
std::queue<uint64_t> bresp;
std::map<uint64_t, std::queue<uint64_t> > wreq;
std::map<uint64_t, std::queue<mm_req_t> > rreq;
std::map<uint64_t, std::queue<mm_rresp_t> > rreq;
std::queue<mm_rresp_t> rresp;
void read_complete(unsigned id, uint64_t address, uint64_t clock_cycle);