make sure dramsim reads and writes occur in the order they are received
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cb2a18b533
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b64998ec05
@ -17,13 +17,12 @@ using namespace DRAMSim;
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void mm_dramsim2_t::read_complete(unsigned id, uint64_t address, uint64_t clock_cycle)
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{
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auto req = rreq[address].front();
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uint64_t start_addr = (address / word_size) * word_size;
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for (int i = 0; i < req.len; i++) {
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auto dat = read(start_addr + i * word_size);
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rresp.push(mm_rresp_t(req.id, dat, (i == req.len - 1)));
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}
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rreq[address].pop();
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mm_rresp_t resp;
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do {
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resp = rreq[address].front();
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rresp.push(resp);
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rreq[address].pop();
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} while (!resp.last);
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}
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void mm_dramsim2_t::write_complete(unsigned id, uint64_t address, uint64_t clock_cycle)
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@ -85,7 +84,11 @@ void mm_dramsim2_t::tick(
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bool b_fire = b_valid() && b_ready;
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if (ar_fire) {
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rreq[ar_addr].push(mm_req_t(ar_id, ar_len + 1, ar_addr));
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uint64_t start_addr = (ar_addr / word_size) * word_size;
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for (int i = 0; i <= ar_len; i++) {
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auto dat = read(start_addr + i * word_size);
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rreq[ar_addr].push(mm_rresp_t(ar_id, dat, (i == ar_len)));
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}
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mem->addTransaction(false, ar_addr);
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}
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@ -9,26 +9,6 @@
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#include <queue>
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#include <stdint.h>
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struct mm_req_t {
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uint64_t id;
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uint64_t len;
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uint64_t addr;
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mm_req_t(uint64_t id, uint64_t len, uint64_t addr)
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{
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this->id = id;
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this->len = len;
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this->addr = addr;
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}
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mm_req_t()
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{
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this->id = 0;
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this->len = 0;
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this->addr = 0;
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}
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};
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class mm_dramsim2_t : public mm_t
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{
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public:
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@ -85,7 +65,7 @@ class mm_dramsim2_t : public mm_t
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std::queue<uint64_t> bresp;
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std::map<uint64_t, std::queue<uint64_t> > wreq;
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std::map<uint64_t, std::queue<mm_req_t> > rreq;
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std::map<uint64_t, std::queue<mm_rresp_t> > rreq;
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std::queue<mm_rresp_t> rresp;
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void read_complete(unsigned id, uint64_t address, uint64_t clock_cycle);
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