add U bit to misa register

2016-07-22 14:22:51 -07:00 · 2016-07-22 14:22:51 -07:00 · 51edd19e85
commit 51edd19e85
parent a43ad522dc
1 changed files with 1 additions and 0 deletions
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@ -238,6 +238,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)

  val isa_string = "IM" +
    (if (usingVM) "S" else "") +
+    (if (usingUser) "U" else "") +
    (if (usingAtomics) "A" else "") +
    (if (usingFPU) "FD" else "") +
    (if (usingRoCC) "X" else "")