make sure Memtest generators write different data to each address
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@ -81,7 +81,7 @@ class UncachedTileLinkGenerator(id: Int)
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val data_prefix = Cat(UInt(id, log2Up(nGens)), req_cnt)
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val word_data = Wire(UInt(width = genWordBits))
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word_data := Cat(data_prefix, full_addr)
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word_data := Cat(data_prefix, part_of_full_addr)
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val beat_data = Fill(tlDataBits / genWordBits, word_data)
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val wshift = Cat(beatOffset(full_addr), UInt(0, wordOffset))
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val wmask = Fill(genWordBits / 8, Bits(1, 1)) << wshift
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@ -151,7 +151,7 @@ class HellaCacheGenerator(id: Int)
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UInt(0, wordOffset)
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}
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val req_addr = UInt(startAddress) + Cat(req_cnt, part_of_req_addr)
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val req_data = Cat(UInt(id, log2Up(nGens)), req_addr)
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val req_data = Cat(UInt(id, log2Up(nGens)), req_cnt, part_of_req_addr)
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io.mem.req.valid := sending && !io.status.finished
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io.mem.req.bits.addr := req_addr
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