start constructing composable tilelink unit test drivers
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Howard Mao
parent
c92732dcaa
commit
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334
groundtest/src/main/scala/unittests/Drivers.scala
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334
groundtest/src/main/scala/unittests/Drivers.scala
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package groundtest.unittests
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import Chisel._
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import junctions._
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import uncore.tilelink._
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import uncore.constants._
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import cde.Parameters
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abstract class Driver(implicit p: Parameters) extends TLModule()(p) {
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val io = new Bundle {
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val mem = new ClientUncachedTileLinkIO
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val start = Bool(INPUT)
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val finished = Bool(OUTPUT)
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}
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}
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/**
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* Tests that single-beat Gets of decreasing size return subsets of the
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* data returned by larger Gets
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*/
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class GetMultiWidthDriver(implicit p: Parameters) extends Driver()(p) {
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val s_start :: s_send :: s_recv :: s_done :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val size = Reg(UInt(width = MT_SZ))
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val ref = Reg(UInt(width = 64))
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val bytemask = MuxLookup(size, UInt(0), Seq(
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MT_D -> UInt("hff"),
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MT_W -> UInt("h0f"),
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MT_H -> UInt("h03"),
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MT_B -> UInt("h01")))
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val bitmask = FillInterleaved(8, bytemask)
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io.mem.acquire.valid := (state === s_send)
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io.mem.acquire.bits := Get(
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client_xact_id = UInt(0),
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addr_block = UInt(0),
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addr_beat = UInt(0),
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addr_byte = UInt(0),
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operand_size = size,
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alloc = Bool(false))
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io.mem.grant.ready := (state === s_recv)
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when (state === s_start && io.start) {
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size := MT_D
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state := s_send
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}
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when (io.mem.acquire.fire()) { state := s_recv }
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when (io.mem.grant.fire()) {
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when (size === MT_D) { ref := io.mem.grant.bits.data }
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size := size - UInt(1)
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state := Mux(size === MT_B, s_done, s_send)
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}
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io.finished := state === s_done
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assert(!io.mem.grant.valid || size === MT_D ||
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(io.mem.grant.bits.data & bitmask) === (ref & bitmask),
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"GetMultiWidth: smaller get does not match larger get")
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}
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/**
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* Tests that single-beat Gets across a range of memory return
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* the expected data.
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* @param expected The values of the data expected to be read.
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* Each element is the data for one beat.
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*/
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class GetSweepDriver(expected: Seq[BigInt])
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(implicit p: Parameters) extends Driver()(p) {
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val s_start :: s_send :: s_recv :: s_done :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val nReqs = expected.size
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val (req_cnt, req_done) = Counter(io.mem.grant.fire(), nReqs)
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when (state === s_start && io.start) { state := s_send }
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when (io.mem.acquire.fire()) { state := s_recv }
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when (io.mem.grant.fire()) { state := s_send }
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when (req_done) { state := s_done }
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val (addr_block, addr_beat) = if (nReqs > tlDataBeats) {
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(req_cnt(log2Up(nReqs) - 1, tlBeatAddrBits),
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req_cnt(tlBeatAddrBits - 1, 0))
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} else {
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(UInt(0), req_cnt)
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}
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val exp_data = Vec(expected.map(e => UInt(e, tlDataBits)))
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io.mem.acquire.valid := (state === s_send)
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io.mem.acquire.bits := Get(
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client_xact_id = UInt(0),
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addr_block = addr_block,
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addr_beat = addr_beat)
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io.mem.grant.ready := (state === s_recv)
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io.finished := state === s_done
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assert(!io.mem.grant.valid || io.mem.grant.bits.data === exp_data(req_cnt),
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"GetSweep: data does not match expected")
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}
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/**
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* Tests that multi-beat GetBlocks across a range of memory return
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* the expected data.
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* @param expected The values of the data expected to be read.
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* Each element is the data for one beat.
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*/
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class GetBlockSweepDriver(expected: Seq[BigInt])
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(implicit p: Parameters) extends Driver()(p) {
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val s_start :: s_send :: s_recv :: s_done :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val nReqs = ((expected.size - 1) / tlDataBeats + 1) * tlDataBeats
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val (req_cnt, req_done) = Counter(io.mem.grant.fire(), nReqs)
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val (addr_beat, beats_done) = Counter(io.mem.grant.fire(), tlDataBeats)
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val tlBlockOffset = tlByteAddrBits + tlBeatAddrBits
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val addr_block =
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if (nReqs > tlDataBeats) req_cnt(log2Up(nReqs) - 1, tlBlockOffset)
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else UInt(0)
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io.mem.acquire.valid := (state === s_send)
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io.mem.acquire.bits := GetBlock(
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client_xact_id = UInt(0),
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addr_block = addr_block)
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io.mem.grant.ready := (state === s_recv)
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io.finished := state === s_done
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when (state === s_start && io.start) { state := s_send }
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when (io.mem.acquire.fire()) { state := s_recv }
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when (beats_done) { state := s_send }
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when (req_done) { state := s_done }
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val exp_data = Vec(expected.map(e => UInt(e, tlDataBits)))
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assert(!io.mem.grant.valid || req_cnt >= UInt(expected.size) ||
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io.mem.grant.bits.data === exp_data(req_cnt),
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"GetBlockSweep: data does not match expected")
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}
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/**
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* Tests that single-beat Puts across a range of memory persists correctly.
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* @param n the number of beats to put
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*/
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class PutSweepDriver(val n: Int)(implicit p: Parameters) extends Driver()(p) {
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val (s_idle :: s_put_req :: s_put_resp ::
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s_get_req :: s_get_resp :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_idle)
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val (put_cnt, put_done) = Counter(state === s_put_resp && io.mem.grant.valid, n)
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val (get_cnt, get_done) = Counter(state === s_get_resp && io.mem.grant.valid, n)
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val (put_block, put_beat) = if (n > tlDataBeats) {
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(put_cnt(log2Up(n) - 1, tlBeatAddrBits),
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put_cnt(tlBeatAddrBits - 1, 0))
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} else {
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(UInt(0), put_cnt)
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}
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val (get_block, get_beat) = if (n > tlDataBeats) {
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(get_cnt(log2Up(n) - 1, tlBeatAddrBits),
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get_cnt(tlBeatAddrBits - 1, 0))
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} else {
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(UInt(0), get_cnt)
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}
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val dataRep = tlDataBits / log2Up(n)
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val put_data = Fill(dataRep, put_cnt)(tlDataBits - 1, 0)
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val get_data = Fill(dataRep, get_cnt)(tlDataBits - 1, 0)
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io.mem.acquire.valid := (state === s_put_req) || (state === s_get_req)
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io.mem.acquire.bits := Mux(state === s_put_req,
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Put(
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client_xact_id = UInt(0),
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addr_block = put_block,
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addr_beat = put_beat,
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data = put_data),
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Get(
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client_xact_id = UInt(0),
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addr_block = get_block,
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addr_beat = get_beat))
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io.mem.grant.ready := (state === s_put_resp) || (state === s_get_resp)
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when (state === s_idle && io.start) { state := s_put_req }
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when (state === s_put_req && io.mem.acquire.ready) { state := s_put_resp }
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when (state === s_put_resp && io.mem.grant.valid) {
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state := Mux(put_done, s_get_req, s_put_req)
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}
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when (state === s_get_req && io.mem.acquire.ready) { state := s_get_resp }
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when (state === s_get_resp && io.mem.grant.valid) {
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state := Mux(get_done, s_done, s_get_req)
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}
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io.finished := (state === s_done)
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assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() ||
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io.mem.grant.bits.data === get_data,
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"PutSweepDriver: data does not match")
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}
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/**
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* Tests that write-masked single-beat puts work correctly by putting
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* data with steadily smaller write-masks to the same beat.
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*/
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class PutMaskDriver(implicit p: Parameters) extends Driver()(p) {
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val (s_idle :: s_put_req :: s_put_resp ::
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s_get_req :: s_get_resp :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_idle)
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val nbytes = Reg(UInt(width = log2Up(tlWriteMaskBits) + 1))
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val wmask = (UInt(1) << nbytes) - UInt(1)
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val wdata = Fill(tlDataBits / 8, Wire(UInt(width = 8), init = nbytes))
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val expected = UInt("h0808080804040201")
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when (state === s_idle && io.start) {
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state := s_put_req
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nbytes := UInt(8)
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}
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when (state === s_put_req && io.mem.acquire.ready) {
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state := s_put_resp
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}
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when (state === s_put_resp && io.mem.grant.valid) {
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nbytes := nbytes >> UInt(1)
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state := Mux(nbytes === UInt(1), s_get_req, s_put_req)
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}
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when (state === s_get_req && io.mem.acquire.ready) {
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state := s_get_resp
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}
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when (state === s_get_resp && io.mem.grant.valid) {
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state := s_done
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}
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io.finished := (state === s_done)
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io.mem.acquire.valid := (state === s_put_req) || (state === s_get_req)
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io.mem.acquire.bits := Mux(state === s_put_req,
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Put(
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client_xact_id = UInt(0),
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addr_block = UInt(0),
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addr_beat = UInt(0),
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data = wdata,
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wmask = Some(wmask)),
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Get(
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client_xact_id = UInt(0),
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addr_block = UInt(0),
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addr_beat = UInt(0)))
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io.mem.grant.ready := (state === s_put_resp) || (state === s_get_resp)
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assert(!io.mem.grant.valid || state =/= s_get_resp ||
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io.mem.grant.bits.data === expected,
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"PutMask: data does not match expected")
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}
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class PutBlockSweepDriver(val n: Int)(implicit p: Parameters)
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extends Driver()(p) {
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val (s_idle :: s_put_req :: s_put_resp ::
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s_get_req :: s_get_resp :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_idle)
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val (put_beat, put_beat_done) = Counter(
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state === s_put_req && io.mem.acquire.ready, tlDataBeats)
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val (put_cnt, put_done) = Counter(
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state === s_put_resp && io.mem.grant.valid, n)
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val (get_beat, get_beat_done) = Counter(
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state === s_get_resp && io.mem.grant.valid, tlDataBeats)
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val (get_cnt, get_done) = Counter(get_beat_done, n)
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val dataRep = tlDataBits / (log2Up(n) + tlBeatAddrBits)
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val put_data = Fill(dataRep, Cat(put_cnt, put_beat))(tlDataBits - 1, 0)
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val get_data = Fill(dataRep, Cat(get_cnt, get_beat))(tlDataBits - 1, 0)
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when (state === s_idle && io.start) { state := s_put_req }
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when (put_beat_done) { state := s_put_resp }
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when (state === s_put_resp && io.mem.grant.valid) {
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state := Mux(put_done, s_get_req, s_put_req)
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}
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when (state === s_get_req && io.mem.acquire.ready) { state := s_get_resp }
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when (get_beat_done) { state := Mux(get_done, s_done, s_get_req) }
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val put_acquire = PutBlock(
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client_xact_id = UInt(0),
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addr_block = put_cnt,
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addr_beat = put_beat,
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data = put_data)
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val get_acquire = GetBlock(
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client_xact_id = UInt(0),
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addr_block = get_cnt)
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io.finished := (state === s_done)
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io.mem.acquire.valid := (state === s_put_req) || (state === s_get_req)
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io.mem.acquire.bits := Mux(state === s_put_req, put_acquire, get_acquire)
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io.mem.grant.ready := (state === s_put_resp) || (state === s_get_resp)
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assert(!io.mem.grant.valid || state =/= s_get_resp ||
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io.mem.grant.bits.data === get_data,
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"PutBlockSweep: data does not match expected")
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}
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class DriverSet(driverGen: Parameters => Seq[Driver])(implicit p: Parameters)
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extends Driver()(p) {
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val s_start :: s_run :: s_done :: Nil = Enum(Bits(), 3)
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val state = Reg(init = s_start)
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val drivers = driverGen(p)
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val idx = Reg(init = UInt(0, log2Up(drivers.size)))
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val finished = Wire(init = Bool(false))
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when (state === s_start && io.start) { state := s_run }
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when (state === s_run && finished) {
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when (idx === UInt(drivers.size - 1)) { state := s_done }
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idx := idx + UInt(1)
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}
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io.finished := state === s_done
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io.mem.acquire.valid := Bool(false)
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io.mem.grant.ready := Bool(false)
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drivers.zipWithIndex.foreach { case (driv, i) =>
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val me = idx === UInt(i)
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driv.io.start := me && state === s_run
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driv.io.mem.acquire.ready := io.mem.acquire.ready && me
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driv.io.mem.grant.valid := io.mem.grant.valid && me
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driv.io.mem.grant.bits := io.mem.grant.bits
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when (me) {
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io.mem.acquire.valid := driv.io.mem.acquire.valid
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io.mem.acquire.bits := driv.io.mem.acquire.bits
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io.mem.grant.ready := driv.io.mem.grant.ready
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finished := driv.io.finished
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}
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}
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}
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