riscv/rocket-chip
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fix up cloneType calls in clock crossers

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This commit is contained in:
Howard Mao
2016-07-13 14:31:19 -07:00
parent eeae74e3fc
commit 66b9c5ad05
1 changed files with 8 additions and 8 deletions
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16
junctions/src/main/scala/crossing.scala
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@@ -2,8 +2,8 @@ package junctions
import Chisel._
class Crossing[T <: Data](gen: T, enq_sync: Boolean, deq_sync: Boolean) extends Bundle {
val enq = Decoupled(gen.cloneType).flip()
val deq = Decoupled(gen.cloneType)
val enq = Decoupled(gen).flip()
val deq = Decoupled(gen)
val enq_clock = if (enq_sync) Some(Clock(INPUT)) else None
val deq_clock = if (deq_sync) Some(Clock(INPUT)) else None
val enq_reset = if (enq_sync) Some(Bool(INPUT)) else None
@@ -24,15 +24,15 @@ class AsyncHandshakeSource[T <: Data](gen: T, sync: Int, clock: Clock, reset: Bo
extends Module(_clock = clock, _reset = reset) {
val io = new Bundle {
// These come from the source clock domain
val enq = Decoupled(gen.cloneType).flip()
val enq = Decoupled(gen).flip()
// These cross to the sink clock domain
val bits = gen.cloneType
val bits = gen.cloneType.asOutput
val push = Bool(OUTPUT)
val pop = Bool(INPUT)
}
val ready = RegInit(Bool(true))
val bits = Reg(gen.cloneType)
val bits = Reg(gen)
val push = RegInit(Bool(false))
io.enq.ready := ready
@@ -57,15 +57,15 @@ class AsyncHandshakeSink[T <: Data](gen: T, sync: Int, clock: Clock, reset: Bool
extends Module(_clock = clock, _reset = reset) {
val io = new Bundle {
// These cross to the source clock domain
val bits = gen.cloneType.flip()
val bits = gen.cloneType.asInput
val push = Bool(INPUT)
val pop = Bool(OUTPUT)
// These go to the sink clock domain
val deq = Decoupled(gen.cloneType)
val deq = Decoupled(gen)
}
val valid = RegInit(Bool(false))
val bits = Reg(gen.cloneType)
val bits = Reg(gen)
val pop = RegInit(Bool(false))
io.deq.valid := valid