riscv/rocket-chip
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get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache

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This commit is contained in:
Howard Mao 2016-07-07 19:01:27 -07:00
parent 32ee5432dd
commit eeac405ef8
4 changed files with 3 additions and 4 deletions
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2
junctions

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Subproject commit 46db745fe3806733257a16766dd97a281810c6d5
Subproject commit 027f3d7fa6bf0da5af899e51a7010921ecb9dff0

2
rocket

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Subproject commit d972677a0c07b6cdf6b806cbd4a152b103c3293c
Subproject commit 5c87faad33ab949af5d8daaa3b3439ceecfd7b83

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src/main/scala/Configs.scala
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@ -308,7 +308,6 @@ class BaseConfig extends Config (
case ConfigString => makeConfigString()
case GlobalAddrMap => globalAddrMap
case EnableL2Logging => false
case NastiResponseBufferDepth => site(MIFDataBeats) * site(NAcquireTransactors)
case _ => throw new CDEMatchError
}},
knobValues = {

2
uncore

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Subproject commit bc6679ecd5edfe8dbfa27e52d06651f7b8ae47dc
Subproject commit 73ef0649f34a2aa3e535ce1eefbb3b81b8c21768