riscv/rocket-chip
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get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache

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Howard Mao
2016-07-07 19:01:27 -07:00
parent 32ee5432dd
commit eeac405ef8
4 changed files with 3 additions and 4 deletions
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2
junctions

Submodule junctions updated: 46db745fe3...027f3d7fa6

2
rocket

Submodule rocket updated: d972677a0c...5c87faad33

1
src/main/scala/Configs.scala
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@ -308,7 +308,6 @@ class BaseConfig extends Config (
case ConfigString => makeConfigString()
case GlobalAddrMap => globalAddrMap
case EnableL2Logging => false
case NastiResponseBufferDepth => site(MIFDataBeats) * site(NAcquireTransactors)
case _ => throw new CDEMatchError
}},
knobValues = {

2
uncore

Submodule uncore updated: bc6679ecd5...73ef0649f3