Andrew Waterman
|
56c4f44c2a
|
hellacache returns!
but AMOs are unimplemented.
|
2011-12-12 06:49:39 -08:00 |
|
Yunsup Lee
|
0ea2704b80
|
new mftx instruction format
|
2011-12-12 03:23:12 -08:00 |
|
Andrew Waterman
|
8308345364
|
work in progress on hellacache
|
2011-12-10 07:01:47 -08:00 |
|
Andrew Waterman
|
ce201559f3
|
Support cache->cpu nacks one cycle after request
|
2011-12-10 00:42:09 -08:00 |
|
Andrew Waterman
|
c01e1f1cef
|
Don't replay from EX stage.
EX replays are now handled from MEM. We may move them to WB.
|
2011-12-09 19:42:58 -08:00 |
|
Andrew Waterman
|
218f63e66e
|
code cleanup/parameterization
|
2011-12-09 00:42:43 -08:00 |
|
Andrew Waterman
|
a87ad06780
|
Automatically infer rocketCAM address width
|
2011-12-06 02:05:40 -08:00 |
|
Rimas Avizienis
|
fa784d1d7d
|
made setReadLatency argument a parameter defined in consts.scala
|
2011-12-05 00:33:17 -08:00 |
|
Rimas Avizienis
|
ff95cacb55
|
icache/dcache tag+data arrays now implemented using Mem4()
however there seems to be a bug - readLatency needs to be set to 0
for C model to work, and 1 for Verilog model.
|
2011-12-04 01:18:38 -08:00 |
|
Rimas Avizienis
|
e894b79870
|
caches now use Mem4() memories for tag+data arrays
|
2011-12-03 19:41:15 -08:00 |
|
Rimas Avizienis
|
c580180b66
|
tweaks to cache/SRAM interface for TSMC65 SRAMs
|
2011-12-02 02:01:08 -08:00 |
|
Rimas Avizienis
|
e70b41241c
|
changed branch addr generation to get it off critical path
|
2011-12-02 01:56:17 -08:00 |
|
Rimas Avizienis
|
cf1965493b
|
renamed SRAM modules to match TSMC65 MC generated SRAMs
|
2011-12-01 13:14:33 -08:00 |
|
Rimas Avizienis
|
da2fdf4f85
|
fixed console i/o
|
2011-11-30 22:51:59 -08:00 |
|
Rimas Avizienis
|
b2894671f6
|
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
|
2011-11-30 21:55:13 -08:00 |
|
Rimas Avizienis
|
bc44572d99
|
bugfixes due to new hcl jar file
|
2011-11-30 21:54:55 -08:00 |
|
Andrew Waterman
|
8f3927fdfa
|
queue data type is now templated
|
2011-11-30 18:08:26 -08:00 |
|
Rimas Avizienis
|
11f0e3daf4
|
more cleanup
|
2011-11-18 00:17:30 -08:00 |
|
Rimas Avizienis
|
c42d8149b7
|
moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
|
2011-11-17 23:50:45 -08:00 |
|
Rimas Avizienis
|
5a322ff00c
|
fixed dtlb bug (swapped r/w permissions), added fake mtfsr/mffsr/fld/fst instructions
|
2011-11-17 11:17:37 -08:00 |
|
Rimas Avizienis
|
80b4253318
|
fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
|
2011-11-16 02:04:28 -08:00 |
|
Rimas Avizienis
|
886857fa47
|
writes of PC weren't being sign extended
|
2011-11-15 18:07:36 -08:00 |
|
Rimas Avizienis
|
fc0f20643a
|
cleanup
|
2011-11-15 18:06:41 -08:00 |
|
Rimas Avizienis
|
ae98956e6b
|
more amo fixes, added more options to testharness to control debug messages
|
2011-11-15 02:43:51 -08:00 |
|
Rimas Avizienis
|
82a636ff55
|
AMOADD, AMOAND, AMOOR, AMOSWAP working
|
2011-11-15 00:51:45 -08:00 |
|
Rimas Avizienis
|
48cec01710
|
updated riscv-bmarks and riscv-tests to build with new toolchain
|
2011-11-15 00:11:22 -08:00 |
|
Rimas Avizienis
|
db87924fbf
|
made eret instruction take an illegal inst exception when ET is set
|
2011-11-14 14:35:10 -08:00 |
|
Rimas Avizienis
|
cd6e463320
|
added ei and di instructions
|
2011-11-14 13:48:49 -08:00 |
|
Rimas Avizienis
|
b791010bb1
|
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
|
2011-11-14 04:13:13 -08:00 |
|
Rimas Avizienis
|
890bfa7c48
|
added IPIs and timer interrupts
|
2011-11-14 03:24:02 -08:00 |
|
Rimas Avizienis
|
5b29765917
|
synced up with supervisor mode state in latest ISA simulator
|
2011-11-14 01:37:20 -08:00 |
|
Rimas Avizienis
|
9d3471a569
|
more cache fixes, more test harness debug output
|
2011-11-13 23:32:18 -08:00 |
|
Rimas Avizienis
|
67c7e7e28f
|
cache/tlb bugfixes, increased memory size to 256meg
|
2011-11-13 13:06:35 -08:00 |
|
Rimas Avizienis
|
29d44b8bc5
|
fixed typo that broke illegal instruction exception
|
2011-11-13 01:17:33 -08:00 |
|
Rimas Avizienis
|
7b3c34a341
|
regenerated instruction encodings using parse-opcodes
|
2011-11-13 00:59:02 -08:00 |
|
Rimas Avizienis
|
44419511b7
|
timer interrupt fixes
|
2011-11-13 00:32:08 -08:00 |
|
Rimas Avizienis
|
345f950eff
|
added timer interrupt support
|
2011-11-13 00:27:57 -08:00 |
|
Rimas Avizienis
|
5f4b15b809
|
added ld/st misaligned exceptions
|
2011-11-13 00:03:17 -08:00 |
|
Rimas Avizienis
|
fbd44ea936
|
added checks for addresses > physical memory size, increased memsize to 64M
|
2011-11-12 23:39:43 -08:00 |
|
Rimas Avizienis
|
35af912bd2
|
cache optimizations, cleanup, and testharness improvement
|
2011-11-12 22:13:29 -08:00 |
|
Rimas Avizienis
|
91c252ad08
|
fixing output enable signals for data/tag SRAMs
|
2011-11-12 15:47:47 -08:00 |
|
Rimas Avizienis
|
83d90c4dab
|
more itlb/dtlb/ptw fixes
|
2011-11-12 15:00:45 -08:00 |
|
Rimas Avizienis
|
73416f224b
|
more tlb/ptw debugging
|
2011-11-12 00:25:06 -08:00 |
|
Rimas Avizienis
|
44926866b7
|
updated itlb
|
2011-11-11 18:48:34 -08:00 |
|
Rimas Avizienis
|
a1ce908541
|
dcache/dtlb overhaul
|
2011-11-11 18:18:47 -08:00 |
|
Rimas Avizienis
|
e4fa94aa27
|
checkpoint
|
2011-11-10 17:41:22 -08:00 |
|
Rimas Avizienis
|
f86d5b1334
|
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
|
2011-11-10 11:26:13 -08:00 |
|
Rimas Avizienis
|
4bd0263a4a
|
added misaligned instruction check, cleaned up badvaddr handling
|
2011-11-10 03:38:59 -08:00 |
|
Rimas Avizienis
|
603ede8bfe
|
access faults now write badvaddr PCR register with faulting address
|
2011-11-10 02:46:09 -08:00 |
|
Rimas Avizienis
|
36aa4bcc9d
|
moved exception handling from ex stage in dpath to mem stage in ctrl
|
2011-11-10 02:26:26 -08:00 |
|