riscv/rocket-chip
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updated itlb

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This commit is contained in:
Rimas Avizienis 2011-11-11 18:48:34 -08:00
parent a1ce908541
commit 44926866b7
4 changed files with 31 additions and 22 deletions
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7
rocket/src/main/scala/cpu.scala
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@ -62,13 +62,14 @@ class rocketProc extends Component
itlb.io.cpu.status := dpath.io.ctrl.status;
itlb.io.cpu.req_val := ctrl.io.imem.req_val;
itlb.io.cpu.req_asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
itlb.io.cpu.req_addr := dpath.io.imem.req_addr;
io.imem.req_val := itlb.io.cpu.resp_val;
io.imem.req_addr := itlb.io.cpu.resp_addr;
dtlb.io.cpu.req_vpn := dpath.io.imem.req_addr(VADDR_BITS-1,PGIDX_BITS);
io.imem.req_vpn := itlb.io.cpu.resp_vpn;
ctrl.io.imem.req_rdy := itlb.io.cpu.req_rdy && io.imem.req_rdy;
ctrl.io.imem.resp_val := io.imem.resp_val;
dpath.io.imem.resp_data := io.imem.resp_data;
ctrl.io.xcpt_itlb := itlb.io.cpu.exception;
ctrl.io.itlb_miss := itlb.io.cpu.resp_miss;
// connect DTLB to D$ arbiter, ctrl+dpath
dtlb.io.cpu.invalidate := Bool(false); // FIXME

3
rocket/src/main/scala/ctrl.scala
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@ -68,6 +68,7 @@ class ioCtrlAll extends Bundle()
val dmem = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "resp_miss")).flip();
val host = new ioHost(List("start"));
val dtlb_miss = Bool('input);
val itlb_miss = Bool('input);
val xcpt_dtlb_ld = Bool('input);
val xcpt_dtlb_st = Bool('input);
val xcpt_itlb = Bool('input);
@ -512,7 +513,7 @@ class rocketCtrl extends Component
io.dpath.stalld := ctrl_stalld.toBool;
io.dpath.killf := take_pc | ~io.imem.resp_val;
io.dpath.killf := take_pc | io.itlb_miss | ~io.imem.resp_val;
io.dpath.killd := ctrl_killd.toBool;
io.dpath.killx := kill_ex.toBool;
io.dpath.killm := kill_mem.toBool;

2
rocket/src/main/scala/dtlb.scala
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@ -60,8 +60,6 @@ class rocketDTLB(entries: Int) extends Component
r_cpu_req_val <== io.cpu.req_val;
}
// val req_vpn = r_cpu_req_addr(VADDR_BITS-1,PGIDX_BITS);
// val req_idx = io.cpu.req_addr(PGIDX_BITS-1,0);
val req_load = (r_cpu_req_cmd === M_XRD);
val req_store = (r_cpu_req_cmd === M_XWR);
// val req_amo = io.cpu.req_cmd(3).toBool;

41
rocket/src/main/scala/itlb.scala
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@ -73,10 +73,11 @@ class ioITLB_CPU(view: List[String] = null) extends Bundle(view)
val req_val = Bool('input);
val req_rdy = Bool('output);
val req_asid = Bits(ASID_BITS, 'input);
val req_addr = UFix(VADDR_BITS, 'input);
val req_vpn = UFix(VPN_BITS, 'input);
// lookup responses
val resp_val = Bool('output);
val resp_addr = UFix(PADDR_BITS, 'output);
val resp_miss = Bool('output);
// val resp_val = Bool('output);
val resp_ppn = UFix(PPN_BITS, 'output);
val exception = Bool('output);
}
@ -93,16 +94,26 @@ class rocketITLB(entries: Int) extends Component
val s_ready :: s_request :: s_wait :: Nil = Enum(3) { UFix() };
val state = Reg(resetVal = s_ready);
val tag_cam = new rocketCAM(entries, addr_bits, ASID_BITS+VPN_BITS);
val req_vpn = io.cpu.req_addr(VADDR_BITS-1,PGIDX_BITS);
val req_idx = io.cpu.req_addr(PGIDX_BITS-1,0);
val lookup_tag = Cat(io.cpu.req_asid, req_vpn);
val r_cpu_req_vpn = Reg(resetVal = Bits(0, VPN_BITS));
val r_cpu_req_val = Reg(resetVal = Bool(false));
val r_cpu_req_cmd = Reg(resetVal = Bits(0,4));
val r_cpu_req_asid = Reg(resetVal = Bits(0,ASID_BITS));
val r_refill_tag = Reg(resetVal = Bits(0, ASID_BITS+VPN_BITS));
val r_refill_waddr = Reg(resetVal = UFix(0, addr_bits));
val repl_count = Reg(resetVal = UFix(0, addr_bits));
when (io.cpu.req_val && io.cpu.req_rdy) {
r_cpu_req_vpn <== io.cpu.req_vpn;
r_cpu_req_asid <== io.cpu.req_asid;
}
when (io.cpu.req_rdy) {
r_cpu_req_val <== io.cpu.req_val;
}
val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
val tag_cam = new rocketCAM(entries, addr_bits, ASID_BITS+VPN_BITS);
val tag_ram = Mem(entries, io.ptw.resp_val, r_refill_waddr.toUFix, io.ptw.resp_ppn);
tag_cam.io.clear := io.cpu.invalidate;
@ -110,7 +121,8 @@ class rocketITLB(entries: Int) extends Component
tag_cam.io.write := io.ptw.resp_val;
tag_cam.io.write_tag := r_refill_tag;
tag_cam.io.write_addr := r_refill_waddr;
val tag_hit_addr = tag_cam.io.hit_addr;
val tag_hit = tag_cam.io.hit;
val tag_hit_addr = tag_cam.io.hit_addr;
// extract fields from status register
val status_s = io.cpu.status(SR_S).toBool; // user/supervisor mode
@ -144,9 +156,8 @@ class rocketITLB(entries: Int) extends Component
val repl_waddr = Mux(invalid_entry, ie_addr, repl_count).toUFix;
val lookup_hit = (state === s_ready) && io.cpu.req_val && tag_cam.io.hit;
val lookup_miss = (state === s_ready) && io.cpu.req_val && !tag_cam.io.hit;
val lookup_hit = (state === s_ready) && r_cpu_req_val && tag_hit;
val lookup_miss = (state === s_ready) && r_cpu_req_val && !tag_hit;
val tlb_hit = status_vm && lookup_hit;
val tlb_miss = status_vm && lookup_miss;
@ -165,10 +176,8 @@ class rocketITLB(entries: Int) extends Component
(status_u && !ux_array(tag_hit_addr).toBool));
io.cpu.req_rdy := (state === s_ready);
io.cpu.resp_val := Mux(status_vm, lookup_hit, io.cpu.req_val);
io.cpu.resp_addr :=
Mux(status_vm, Cat(tag_ram(tag_hit_addr), req_idx),
io.cpu.req_addr(PADDR_BITS-1,0)).toUFix;
io.cpu.resp_miss := tlb_miss;
io.cpu.resp_ppn := Mux(status_vm, tag_ram(tag_hit_addr), r_cpu_req_vpn(PPN_BITS-1,0)).toUFix;
io.ptw.req_val := (state === s_request);
io.ptw.req_vpn := r_refill_tag(VPN_BITS-1,0);