fixing output enable signals for data/tag SRAMs
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83d90c4dab
commit
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@ -202,6 +202,7 @@ class rocketDCacheDM(lines: Int) extends Component {
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val p_store_valid = Reg(resetVal = Bool(false));
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val req_store = (io.cpu.req_cmd === M_XWR);
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val req_load = (io.cpu.req_cmd === M_XRD) || (io.cpu.req_cmd === M_PRD);
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val r_req_load = (r_cpu_req_cmd === M_XRD) || (r_cpu_req_cmd === M_PRD);
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val r_req_store = (r_cpu_req_cmd === M_XWR);
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val r_req_flush = (r_cpu_req_cmd === M_FLA);
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@ -327,7 +328,14 @@ class rocketDCacheDM(lines: Int) extends Component {
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data_array.io.d := Mux((state === s_refill), io.mem.resp_data, store_data);
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data_array.io.we := ((state === s_refill) && io.mem.resp_val) || drain_store || resolve_store;
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data_array.io.bweb := Mux((state === s_refill), ~Bits(0,128), store_wmask);
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data_array.io.ce := Bool(true); // FIXME
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// data_array.io.ce := Bool(true); // FIXME
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data_array.io.ce :=
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(io.cpu.req_val && io.cpu.req_rdy && req_load) ||
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(state === s_start_writeback) ||
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(state === s_writeback) ||
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((state === s_resolve_miss) && r_req_load) ||
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(state === s_replay_load);
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val data_array_rdata = data_array.io.q;
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// signal a load miss when the data isn't present in the cache and when it's in the pending store data register
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@ -73,7 +73,7 @@ class rocketDTLB(entries: Int) extends Component
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tag_cam.io.clear := io.cpu.invalidate;
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tag_cam.io.tag := lookup_tag;
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tag_cam.io.write := io.ptw.resp_val;
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tag_cam.io.write := io.ptw.resp_val || io.ptw.resp_err;
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tag_cam.io.write_tag := r_refill_tag;
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tag_cam.io.write_addr := r_refill_waddr;
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val tag_hit = tag_cam.io.hit;
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@ -117,7 +117,7 @@ class rocketITLB(entries: Int) extends Component
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tag_cam.io.clear := io.cpu.invalidate;
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tag_cam.io.tag := lookup_tag;
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tag_cam.io.write := io.ptw.resp_val;
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tag_cam.io.write := io.ptw.resp_val || io.ptw.resp_err;
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tag_cam.io.write_tag := r_refill_tag;
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tag_cam.io.write_addr := r_refill_waddr;
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val tag_hit = tag_cam.io.hit;
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