riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
64 Commits 1 Branch 0 Tags 13 MiB
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%
ff95cacb55
Go to file
Rimas Avizienis ff95cacb55 icache/dcache tag+data arrays now implemented using Mem4() 
however there seems to be a bug - readLatency needs to be set to 0
for C model to work, and 1 for Verilog model.
2011-12-04 01:18:38 -08:00
rocket/src/main/scala icache/dcache tag+data arrays now implemented using Mem4() 2011-12-04 01:18:38 -08:00