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riscv
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rocket-chip
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5f4b15b809888bd5f9b44cdadfcc0aa40c38688f
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Rimas Avizienis
5f4b15b809
added ld/st misaligned exceptions
2011-11-13 00:03:17 -08:00
rocket/src/main
/scala
added ld/st misaligned exceptions
2011-11-13 00:03:17 -08:00
Description
Rocket Chip Generator (
https://github.com/freechipsproject/rocket-chip
)
13
MiB
Languages
Scala
93.1%
C++
2.1%
Python
2%
Makefile
1.2%
Verilog
0.8%
Other
0.7%