riscv/rocket-chip
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Author SHA1 Message Date
Christopher CelioandGitHub c4978712c9 csr: allow for superscalar decode (#1069) 
* CSR provides a decode port to check for an illegal instruction.
   * This commit now allows for multiple instructions in decode to get this
      illegal instruction information.
   * This commit leverages the existing decodeWidth parameter. This will
      potentially over-provision the number of decode ports needed for
      RVC-enabled cores.

Closes #1068
 2017-10-25 13:58:26 -07:00
Christopher CelioandAndrew Waterman 3fe00ce32a Update README.md 
- Removed instruction to checkout riscv-tests (as they are now globally installed when building the riscv-tools).
- Clarified the riscv-tools set-up information to clarify that the rocket-chip/riscv-tools is the version to build.
 2016-05-10 22:12:02 -07:00
Christopher CelioandAndrew Waterman 2d6f35525e Added Field[Int] to SFMALatency/DFMALatency params 2016-04-06 14:50:57 -07:00
Christopher CelioandAndrew Waterman 1792d01ce1 fix leaky assert in nbdcache 
Squash of #33.
 2016-03-31 15:56:14 -07:00
Christopher Celio f526d380fd separate btb response mask from the frontend mask 
It is now the job of the pipeline to monitor the frontend's valid mask (of
instructions) and the BTB's suggested valid mask (based on the prediction it
makes). Some processors may want to ignore or override the BTB's prediction and
thus can supply their own instruction mask.
 2016-03-26 05:37:26 -07:00
Christopher Celio 8687ce5ebd bump torture 2016-02-16 15:13:59 -08:00
Christopher Celio 2e15d92d18 bump torture 2016-02-16 14:24:31 -08:00
Christopher Celio c1b4d9372f Revert "add new parameters for new SCR file" 
This reverts commit 4dad5b8b32.

The commit breaks the build.
 2016-02-13 04:02:20 -08:00
Christopher Celio 6c6bbca92a Revert "use singleton for global" 
This reverts commit 4d0f941de3.

The commit breaks the build.
 2016-02-13 03:56:47 -08:00
Christopher Celio b96343a4e5 [btb] fix mix type error for fetch-width > 1 
closes #24
 2016-02-08 17:41:38 -08:00
Christopher Celio 31dd311aff [fpu] fix rounding mode bug in fdivfsqrt 2016-02-08 17:38:31 -08:00
Christopher Celio 76bf1da310 [commitlog] zero-extend SP write-back values 2015-09-15 16:47:26 -07:00
Christopher Celio e22bf02a80 [commitlog] CSR's cycle optionally set to instret 
- Allows debugging Rocket against Spike by having timer interrupts
    occur in the same place in the instruction stream for both.
 2015-09-15 16:47:26 -07:00
Christopher Celio 7d14abf262 [commitlog] Added privilege-level to output 2015-09-15 16:47:24 -07:00
Christopher Celio 53a02a62c8 [commitlog] Fix sp/dp bug in FPU writeback 2015-09-15 16:46:47 -07:00
Christopher Celio d630a03857 [commitlog] Added FP instructions to the commitlog 2015-09-15 15:59:13 -07:00
Christopher Celio 91458bef1c [commitlog] Initial commit log for integer working 2015-09-15 15:59:03 -07:00
Christopher Celio 754c47bdd1 Removed "make debug" test from travis 
- currently causes gcc4.8 to crash
  - likely due to high memory requirements in compiling generated c++
    code for debug/vcd output
 2015-09-14 15:45:50 -07:00
Christopher Celio c2344ee2bc Added generated-src-debug to make clean target 2015-09-11 19:07:33 -07:00
Christopher Celio c9d89226fb Generated *.d file of tests now kept in order 
-Changed Set to LinkedHashSet in Testing.scala
 2015-09-11 18:36:04 -07:00
Christopher Celio c8a7deb950 Added a commitlog post-processor for Rocket 
- Useful for taking Rocket's out-of-order writebacks and generating an
    in-order commit log.
  - Resulting commit log can be diffed against Spike's commit log.
 2015-09-11 16:06:01 -07:00
Christopher Celio 17e971bbfa Add emulator "make debug" and "-j" to travis 2015-09-10 17:34:16 -07:00
Christopher Celio d9a2162472 Bump Chisel 2015-09-10 17:26:41 -07:00
Christopher Celio 8f71c4da2d Reintroduced multiple emulator backend directories 
Fixes a "make -j" concurrency bug due to deleting files that another
  parallel rule depends on.
 2015-09-10 17:14:23 -07:00
Christopher Celio 83df4bcc35 Fixed run-bmark-tests make target in vsim 2015-09-09 22:37:47 -07:00
Christopher Celio e6b6ff5a1d Update README.md 
Corrected PublicConfigs.scala -> Configs.scala
 2015-09-02 22:55:53 -07:00
Christopher Celio b55765f597 Bump riscv-tools 2015-08-26 16:08:45 -07:00
Christopher Celio b1e845f370 Add space to README.md 2015-08-26 14:34:22 -07:00
Christopher Celio b09832f1b5 ICache now returns the "next PC" signal. 
useful for other modules that need access to the fetch PC on the
   cycle it is sent to the SRAM.
 2015-05-07 04:53:05 -07:00
Christopher Celio 517d0d4b89 feedback on PR 2015-04-12 18:44:03 -07:00
Christopher Celio 4d6ebded02 Added assert to nbdcache 2015-04-11 02:58:34 -07:00
Christopher Celio a564f08702 Rename dmem.sret signal to more accurate invalidate_lr 2015-04-11 02:26:33 -07:00
Christopher Celio 8fc2d38ca9 Removed unnecessary signal in CSRIO 2015-04-11 02:20:34 -07:00
Christopher Celio 2f88c5ca9d Renamed PCR to CSR 2015-04-11 02:16:44 -07:00
Christopher Celio 11dbd4221a Fixed front-end to support four-wide fetch. 2015-04-10 17:53:47 -07:00
Christopher Celio 06dea3790a Removed sret from ptw; sret now comes thru io.cpu to dcache 2015-03-03 16:50:41 -08:00
Christopher Celio 5d07733057 Removed TLBPTWIO from the io.cpu bundle for icache/dcache 2015-03-03 16:40:39 -08:00
Christopher Celio f19b3ca43e Deleted extra spaces at EOL in ctrl.scala 2014-11-16 22:04:33 -08:00
Christopher Celio 6749f67b7f Fixed BHT update error. 
- separated out BTB/BHT update
   - BHT updates counters on every branch
   - BTB update only on mispredicted and taken branches
 2014-11-16 22:02:27 -08:00
Christopher Celio fea31d2167 Significant changes and fixes to BTB for superscalar fetch. 
- BTBUpdate only occurs on mispredicts now.
   - RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
      Decode).
   - Added optional 2nd CAM port to BTB for updates (for when updates to the
      BTB may occur out-of-order).
   - Fixed resp.mask bit logic.
 2014-11-11 03:34:05 -08:00
Christopher Celio 3be3cd7731 Fixed error with icache/btb resp mask. 2014-11-03 01:13:22 -08:00
Christopher Celio 08d2c13330 Fixed btb/icache bugs regarding resp mask, fw==1 2014-10-20 18:45:23 -07:00
Christopher Celio 91efdc379b Merge remote-tracking branch 'origin/master' into ss-frontend 
Also fixed bridx logic and zero-width wire logic.

Conflicts:
	src/main/scala/btb.scala
 2014-10-14 18:10:29 -07:00
Christopher Celio 59eb7d194d Finalize superscalar btb. 2014-10-03 16:08:08 -07:00
Christopher Celio 99614e37aa Merge remote-tracking branch 'origin/master' into ss-frontend 
Conflicts:
	src/main/scala/btb.scala
	src/main/scala/core.scala
 2014-10-03 04:22:58 -07:00
Christopher Celio 9cc35dee9a Returned history update to fetch. 
- Global history only contains branches.
   - Only update BHT and history on BTB hits.
   - Gate off speculative update on stall or icmiss.
   - Fixed bug where BHT updates were delayed a cycle.
 2014-09-29 21:41:07 -07:00
Christopher Celio 8ccd07cfeb Moved updating global history from fetch to decode. 
- No longer update global history in fetch stage.
   - Only update global history when instruction is a branch.
   - Does allow for the possibility of back-to-back branches to see
     slightly different histories on subsequent executions.
 2014-09-28 05:16:36 -07:00
Christopher Celio 681b43f398 Bug fixes with global history register. 
- Updated in fetch speculatively.
      * Updates gated off by cpu.resp.fire().
      * BTB direction factored into history update.
   - All branches update the BHT.
   - Each instruction carries history; index into BHT is recomputed by
     passing in mem_reg_pc.
 2014-09-26 10:39:57 -07:00
Christopher Celio a71bdbbc54 Update history register in fetch speculatively 2014-09-26 05:42:08 -07:00
Christopher Celio f917810061 Removed RocketCoreParameters from use. 
- The nbdache (among others?) use CoreParameters, which has nothing to do with RetireWidth requirements.
   - This conflicts with other cores which uses nbdcache.
   - RocketCoreParameters may be unneccessary, and the require() check can be moved deeper into Rocket.
 2014-09-26 05:14:50 -07:00
Christopher Celio 868e747656 Factored out Rocket specifics from CoreParameters 
- Added new RocketCoreParameters
   - Other cores using Rocket as a library will no longer conflict against
      Rocket's requires().
 2014-09-25 18:52:58 -07:00
Christopher Celio 180d3d365d Expanded front-end to support superscalar fetch. 2014-09-17 14:24:03 -07:00
Christopher Celio fc52840ce2 move timeout in Makefile to a variable 2014-01-31 16:52:59 -08:00
Christopher Celio a2be21361e Allow ICacheConfig to toggle fetch-width. 2014-01-22 16:19:57 -08:00
Christopher Celio 1be9d15944 Fixed bug regarding case sensitivity regarding ioICache,ioDCache 2012-02-07 14:07:42 -08:00