Christopher Celio e22bf02a80 [commitlog] CSR's cycle optionally set to instret ...

- Allows debugging Rocket against Spike by having timer interrupts
    occur in the same place in the instruction stream for both.

2015-09-15 16:47:26 -07:00

rocket

[commitlog] CSR's cycle optionally set to instret

2015-09-15 16:47:26 -07:00

S

Description

Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)

13 MiB

Languages

Scala 93.1%

C++ 2.1%

Python 2%

Makefile 1.2%

Verilog 0.8%

Other 0.7%