riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Update README.md

Browse Source 
Corrected PublicConfigs.scala -> Configs.scala
This commit is contained in:
Christopher Celio 2015-09-02 22:55:53 -07:00
parent 1bfd873888
commit e6b6ff5a1d
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
README.md
View File

@ -159,7 +159,7 @@ module name), which instantiates a Rocket core, uncore logic, and glues
them together.
* **Network.scala**: This source file holds the crossbar network used in
the uncore for multi-core implementations.
* **PublicConfigs.scala**: This holds all the rocket-chip parameters.
* **Configs.scala**: This holds all the rocket-chip parameters.
Probably this file is the most important file for external users. We
will revisit this topic in the next section "How should I use the Rocket
chip generator?", and will also post a more detailed explanation of the
@ -398,7 +398,7 @@ tests and benchmarks.
By now, you probably figured out that all generated files have a
configuration name attached, e.g. DefaultCPPConfig and
DefaultVLSIConfig. Take a look at src/main/scala/PublicConfigs.scala.
DefaultVLSIConfig. Take a look at src/main/scala/Configs.scala.
Search for NSets and NWays defined in DefaultConfig. You can change
those numbers to get a Rocket core with different cache parameters. For
example, by changing L1I, NWays to 4, you will get a 32KB 4-way