[commitlog] Added privilege-level to output
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@ -386,7 +386,7 @@ class FPU extends CoreModule
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when (load_wb) {
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regfile(load_wb_tag) := load_wb_data_recoded
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if (EnableCommitLog) {
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printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data) // TODO see what happens, either change spike to sext, or us or whatever.
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printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data)
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}
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}
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@ -502,20 +502,20 @@ class Rocket extends CoreModule
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val wfd = wb_ctrl.wfd
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val wxd = wb_ctrl.wxd
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val has_data = wb_wen && !wb_set_sboard
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val priv = csr.io.status.prv
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when (wb_valid) {
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// TODO add privileged level
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when (wfd) {
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printf ("0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", pc, inst, rd, rd+UInt(32))
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printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd+UInt(32))
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}
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.elsewhen (wxd && rd != UInt(0) && has_data) {
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printf ("0x%x (0x%x) x%d 0x%x\n", pc, inst, rd, rf_wdata)
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printf ("%d 0x%x (0x%x) x%d 0x%x\n", priv, pc, inst, rd, rf_wdata)
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}
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.elsewhen (wxd && rd != UInt(0) && !has_data) {
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printf ("0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", pc, inst, rd, rd)
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printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd)
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}
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.otherwise { // !wxd || (wxd && rd == 0)
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printf ("0x%x (0x%x)\n", pc, inst)
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printf ("%d 0x%x (0x%x)\n", priv, pc, inst)
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}
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}
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