[commitlog] Initial commit log for integer working
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78b2e947de
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@ -492,12 +492,46 @@ class Rocket extends CoreModule
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io.rocc.cmd.bits.rs1 := wb_reg_wdata
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io.rocc.cmd.bits.rs2 := wb_reg_rs2
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printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
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val COMMITLOG = true
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if (COMMITLOG) {
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val pc = Wire(SInt(width=64))
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pc := wb_reg_pc//.toSInt()
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val inst = wb_reg_inst
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val rd = RegNext(RegNext(RegNext(id_waddr)))
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val wfd = wb_ctrl.wfd
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val wxd = wb_ctrl.wxd
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val has_data = wb_wen && !wb_set_sboard
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when (wb_valid) {
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// TODO add privileged level
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when (wfd) {
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printf ("0x%x (0x%x) f%d\n", pc, inst, rd)
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}
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.elsewhen (wxd && rd != UInt(0) && has_data) {
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printf ("0x%x (0x%x) x%d 0x%x\n", pc, inst, rd, rf_wdata)
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}
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.elsewhen (wxd && rd != UInt(0) && !has_data) {
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printf ("0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", pc, inst, rd, rd)
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}
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.otherwise { // !wxd || (wxd && rd == 0)
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printf ("0x%x (0x%x)\n", pc, inst)
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}
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}
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// ll write data
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when (ll_wen) {
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printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata)
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}
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}
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else {
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printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
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io.host.id, csr.io.time(32,0), wb_valid, wb_reg_pc,
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Mux(rf_wen, rf_waddr, UInt(0)), rf_wdata, rf_wen,
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wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
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wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),
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wb_reg_inst, wb_reg_inst)
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}
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def checkExceptions(x: Seq[(Bool, UInt)]) =
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(x.map(_._1).reduce(_||_), PriorityMux(x))
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