Henry Cook
5bc6981414
fix metadata default, add bug TODO
2014-05-06 18:36:22 -07:00
Henry Cook
7d6a642c0c
correct use of function value to initialize MetaDataArray
2014-05-06 13:00:00 -07:00
Henry Cook
7f690dd9c8
parameterize metadataarray
2014-05-01 01:45:45 -07:00
Henry Cook
519b2ea2b6
New metadata result trait
2014-04-26 19:08:56 -07:00
Henry Cook
1b156c6db9
TileLinkIO.GrantAck -> TileLinkIO.Finish
2014-04-26 15:18:21 -07:00
Henry Cook
fc825c7103
MetaData & friends moved to uncore/
2014-04-23 16:23:51 -07:00
Henry Cook
f4d326b8d7
Prep in HellaCache for extracting MetaData to uncore
2014-04-23 15:43:31 -07:00
Henry Cook
5c62cff2ce
put replacement policy in uncore and minor nbdcache cleanups
2014-04-22 16:53:20 -07:00
Andrew Waterman
09e2ec1f9e
Fix sign of remainder when dividing by zero
...
h/t chris
2014-04-18 16:32:57 -07:00
Henry Cook
1fa505f9ff
remove superfluous AVec object
2014-04-16 17:19:32 -07:00
Andrew Waterman
3520620fbd
Remove D$ -> BTB path
2014-04-15 23:05:02 -07:00
Andrew Waterman
de492b3cf7
Fix critical path through integer scoreboard
2014-04-15 21:28:13 -07:00
Henry Cook
444d0449e3
io.cnt bug in serializer
2014-04-14 17:13:13 -07:00
Henry Cook
1da8ef2ddf
Added serdes to decouple cache row size from tilelink data size
2014-04-10 12:34:12 -07:00
Henry Cook
910b3b203a
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
2014-04-10 12:32:44 -07:00
Henry Cook
ebdc0a2692
merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
2014-04-10 12:09:52 -07:00
Stephen Twigg
e90f2484aa
Sync with riscv-opcodes (csr register mapping)
2014-04-08 15:48:37 -07:00
Andrew Waterman
3ed8adf032
Add early out for MUL[W] (not MULH[[S]U])
2014-04-07 23:48:02 -07:00
Andrew Waterman
927287da34
Bypass RAS push/pop
2014-04-07 23:47:53 -07:00
Andrew Waterman
f235fa0db6
Move branch resolution to M stage
2014-04-07 15:58:49 -07:00
Andrew Waterman
db59fc65ab
Add return address stack
2014-04-01 15:01:27 -07:00
Andrew Waterman
e3b12e0b85
Make BTB more complexity-effective
...
BTB entries reference a small number of unique pages, so we separate the
storage of pages from indices. This makes much larger BTBs feasible. It's
easy to exacerbate cycle time this way, so one-hot encoding is used as needed.
2014-03-25 05:22:04 -07:00
Andrew Waterman
804b09c8c5
Frontend QoR tweaks
2014-03-25 05:20:24 -07:00
Andrew Waterman
6465e2df14
Make Int -> Bool conversions explicit
2014-03-24 04:36:53 -07:00
Andrew Waterman
1b030777ce
Remove vestigial control signal
2014-03-24 04:36:12 -07:00
Andrew Waterman
5996418021
Fix exception behavior of fmin/fmax
2014-03-18 18:36:51 -07:00
Andrew Waterman
54cbf0c4f1
Add (unused) RV32 CSRs
2014-03-15 17:33:17 -07:00
Andrew Waterman
943d7ac80a
Use LinkedHashSet/Map for simpler determinism
2014-03-15 17:31:48 -07:00
Donggyu Kim
53d62cb69d
remove nondeterminism
2014-03-15 16:45:58 -07:00
Andrew Waterman
a0389645b7
New FP encoding; improved FP implementation
2014-03-11 18:58:24 -07:00
Andrew Waterman
00bc1a2293
Add fclass.{s|d} instructions
2014-03-10 16:59:24 -07:00
Yunsup Lee
ac4b3f9f22
print out core id
2014-03-04 23:38:49 -08:00
Andrew Waterman
9f2e16c58a
Fix D$ arbiter for >2 inputs
2014-03-04 16:32:17 -08:00
Andrew Waterman
fa75f6e81e
Fix null pointer exception when HAS_FPU=false
2014-03-04 16:32:09 -08:00
Andrew Waterman
c7110c8389
Make FPU pipeline depths configurable
2014-02-28 13:39:59 -08:00
Yunsup Lee
98b830201a
add wen signal to dasm printf
2014-02-25 03:31:06 -08:00
Yunsup Lee
97b1841fcf
change dcache tag bits to 7
2014-02-22 22:53:04 -08:00
Andrew Waterman
8e3ca609f7
Renumber uarch CSRs into custom CSR space
2014-02-14 17:40:00 -08:00
Andrew Waterman
a09ff9fdc7
Revert to old AUIPC definition
2014-02-10 19:04:42 -08:00
Andrew Waterman
1456170c6d
Always stall decode on RoCC -> FENCE; never stall on RoCC -> deferred AMO.RL fence
2014-02-06 12:01:49 -08:00
Andrew Waterman
eca8c99f44
Ignore rocc interrupt line when no rocc is present
2014-02-06 03:06:55 -08:00
Andrew Waterman
e7a726fbac
Make uarch counters read-only
2014-02-06 01:48:56 -08:00
Quan Nguyen
f021213b1d
Merge remote-tracking branch 'origin/master' into hwacha-port
2014-02-06 00:21:28 -08:00
Andrew Waterman
62e9313aef
Add 16 microarchitectural counters
2014-02-06 00:13:02 -08:00
Yunsup Lee
ff7cae29f7
hookup rocc interrupt and s bit
2014-02-06 00:09:42 -08:00
Yunsup Lee
ab4a3e937b
don't share fma pipes
2014-02-05 14:21:43 -08:00
Stephen Twigg
6a02d15c21
Merge branch 'master' into hwacha-port
2014-02-04 17:05:03 -08:00
Henry Cook
2c2b3a7678
cleanups supporting uncore hierarchy
2014-01-31 12:07:26 -08:00
Andrew Waterman
febd26f505
Correct CSR privilege logic
2014-01-31 01:03:17 -08:00
Stephen Twigg
3c3c469725
Add exception signal to rocc interface
2014-01-28 22:13:16 -08:00
