hookup rocc interrupt and s bit
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@ -745,4 +745,5 @@ class Control(implicit conf: RocketConfiguration) extends Module
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io.rocc.cmd.valid := wb_rocc_val
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io.rocc.exception := wb_reg_xcpt && sr.er
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io.rocc.s := sr.s
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}
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@ -190,6 +190,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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pcr.io.host <> io.host
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pcr.io <> io.ctrl
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pcr.io <> io.fpu
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pcr.io.rocc <> io.rocc
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pcr.io.pc := wb_reg_pc
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io.ctrl.csr_replay := pcr.io.replay
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@ -108,6 +108,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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val time = UInt(OUTPUT, conf.xprlen)
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val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
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val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
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val rocc = new RoCCInterface().flip
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}
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val reg_epc = Reg(Bits(width = VADDR_BITS+1))
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@ -168,8 +169,8 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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val wdata = Mux(cpu_req_valid, io.rw.wdata, host_pcr_bits.data)
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io.status := reg_status
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io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false),
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Bool(false), Bool(false), Bool(false), Bool(false))
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io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false),
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Bool(false), io.rocc.interrupt, Bool(false), Bool(false))
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io.fatc := wen && decoded_addr(CSRs.fatc)
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io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt
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io.ptbr := reg_ptbr
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@ -39,6 +39,7 @@ class RoCCInterface(implicit conf: RocketConfiguration) extends Bundle
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val resp = Decoupled(new RoCCResponse)
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val mem = new HellaCacheIO()(conf.dcache)
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val busy = Bool(OUTPUT)
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val s = Bool(INPUT)
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val interrupt = Bool(OUTPUT)
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// These should be handled differently, eventually
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