riscv/rocket-chip
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79 Commits

Author SHA1 Message Date
Henry Cook
84576650b5 Removed all traces of params 2015-10-05 21:48:05 -07:00
Andrew Waterman
52fc34a138 Chisel3: bulk connect is not commutative 
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with.  Should make
for lively debate.
 2015-08-01 21:11:25 -07:00
Andrew Waterman
cc447c8110 Refactor pipeline RTL (merge ctrl + dpath into rocket) 2015-07-21 17:10:56 -07:00
Henry Cook
3048f4785a HeaderlessTileLinkIO -> ClientTileLinkIO 2015-04-17 16:56:53 -07:00
Henry Cook
91e882e3f8 Use HeaderlessTileLinkIO 2015-04-13 15:58:10 -07:00
Christopher Celio
a564f08702 Rename dmem.sret signal to more accurate invalidate_lr 2015-04-11 02:26:33 -07:00
Yunsup Lee
ebbd14254c uncached port should be a HeaderlessUncachedTileLinkIO type 2015-03-13 02:12:23 -07:00
Henry Cook
51e4cd7616 Added UncachedTileLinkIO port to RocketTile, simplify arbitration 2015-03-12 16:30:04 -07:00
Henry Cook
95aa295c39 Use HeaderlessTileLinkIO to cut down on unconnected port errors in VCS 2015-03-09 16:34:43 -07:00
Henry Cook
b36d751250 sret bugfix: bypass arbiter 2015-03-05 13:14:16 -08:00
Christopher Celio
5d07733057 Removed TLBPTWIO from the io.cpu bundle for icache/dcache 2015-03-03 16:40:39 -08:00
Henry Cook
c9320862ae add l2 dmem signal to rocc 2014-12-12 16:55:08 -08:00
Adam Izraelevitz
3e256439c9 Add abstract class Tile 2014-09-24 13:04:20 -07:00
Yunsup Lee
8abf62fae3 add LICENSE 2014-09-12 18:06:41 -07:00
Henry Cook
5eb5e9eaf5 Standardize ()=>Module(...) top-level Parameters 2014-09-07 17:54:41 -07:00
Henry Cook
b42a2ab40a Final parameter refactor 2014-09-01 13:28:58 -07:00
Henry Cook
2de268b3b1 Cache utility traits. Completely compiles, asm tests hang. 2014-08-19 11:38:20 -07:00
Henry Cook
ca5f38ff26 a few more fixes. some param lookups fail (here() in Alter blocks) 2014-08-19 11:38:11 -07:00
Henry Cook
0dac9a7467 Full conversion to params. Compiles but does not elaborate. 2014-08-19 11:38:02 -07:00
Adam Izraelevitz
812353bace Ported FPU parameters to new Chisel Parameters 2014-08-19 11:37:27 -07:00
Andrew Waterman
04593d433e clean up Int <-> Boolean conversion stuff 2014-06-14 13:58:07 -07:00
Henry Cook
1b156c6db9 TileLinkIO.GrantAck -> TileLinkIO.Finish 2014-04-26 15:18:21 -07:00
Henry Cook
910b3b203a removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants 2014-04-10 12:32:44 -07:00
Henry Cook
ebdc0a2692 merge Aqcuire and AcquireData. cache line size coupled to tilelink data size 2014-04-10 12:09:52 -07:00
Andrew Waterman
c7110c8389 Make FPU pipeline depths configurable 2014-02-28 13:39:59 -08:00
Yunsup Lee
97b1841fcf change dcache tag bits to 7 2014-02-22 22:53:04 -08:00
Stephen Twigg
6a02d15c21 Merge branch 'master' into hwacha-port 2014-02-04 17:05:03 -08:00
Henry Cook
2c2b3a7678 cleanups supporting uncore hierarchy 2014-01-31 12:07:26 -08:00
Andrew Waterman
0266c1f76a Support retirement width > 1 in CSR file 2014-01-24 16:37:40 -08:00
Yunsup Lee
6bbbf36979 push accel/rocket dmem port back to rocket 2014-01-16 16:01:41 -08:00
Quan Nguyen
ebec444ad2 Increase tag width for configurable precision in Hwacha 2013-12-13 03:33:02 -08:00
Yunsup Lee
4c56323f6f hookup all memory ports 2013-11-05 17:12:09 -08:00
Stephen Twigg
eae571e371 Remove rocc memory simplifye module (Hwacha has its own) 2013-11-05 15:31:03 -08:00
Stephen Twigg
36b85b8ee2 Fix issue where the MSB of D$ req tag was getting lost for all agents when an accelerator was attached. 2013-09-25 11:51:10 -07:00
Andrew Waterman
81c752de84 Support disabling virtual memory 2013-09-24 13:58:47 -07:00
Andrew Waterman
f12bbc1e43 working RoCC AccumulatorExample 2013-09-14 22:34:53 -07:00
Andrew Waterman
d053bdc89f Remove Hwacha from Rocket 
Soon it will use the coprocessor interface.
 2013-09-12 22:34:38 -07:00
Andrew Waterman
d4a0db4575 Reflect ISA changes 2013-08-24 14:43:55 -07:00
Henry Cook
ae02ebd153 Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2 
Conflicts:
	src/core.scala
	src/ctrl.scala
	src/dpath_util.scala
	src/fpu.scala
	src/nbdcache.scala
	src/tile.scala
 2013-08-15 16:35:27 -07:00
Henry Cook
b570435847 Reg standardization 2013-08-13 17:50:02 -07:00
Henry Cook
858169917e removed dummy DNCs handled by pruning 2013-08-12 22:34:46 -07:00
Huy Vo
387cf0ebe0 reset -> resetVal, getReset -> reset 2013-08-12 20:51:54 -07:00
Henry Cook
1a9e43aa11 initial attempt at upgrade 2013-08-12 10:39:11 -07:00
Henry Cook
4eaab214d2 Fold uncore constants into TileLinkConfiguration, update coherence API 2013-08-02 16:29:51 -07:00
Henry Cook
9abdf4e154 Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object. 2013-07-23 20:27:58 -07:00
Henry Cook
5c00d0a030 new tilelink arbiter type 2013-07-09 15:31:46 -07:00
Henry Cook
69b508ff39 ported caches and htif to use new tilelink 2013-05-21 17:21:04 -07:00
Henry Cook
16113a96ba fixes after merge 2013-03-25 19:09:08 -07:00
Henry Cook
95f0a688e9 Merge branch 'release-xacts' 
Conflicts:
	src/htif.scala
	src/icache.scala
	src/nbdcache.scala
	src/tile.scala
 2013-03-20 17:37:50 -07:00
Henry Cook
273bd34091 Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants. 2013-03-20 15:53:36 -07:00