riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,134 Commits 1 Branch 0 Tags 13 MiB
5efd38bf97
Commit Graph

4134 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Andrew Waterman
e2755a0f0a Work around zero-width wire limitation in HTIF 2016-05-25 20:39:53 -07:00
Andrew Waterman
3e238adc67 rtc: fix acquire message type check 2016-05-25 20:37:48 -07:00
Andrew Waterman
40f38dde63 Work around lack of zero-width wires in D$ 2016-05-25 19:44:31 -07:00
Wesley W. Terpstra
976d4d3184 ahb: AHB parameters should match TileLink parameters by default 
Closes #116
 2016-05-25 18:01:25 -07:00
Andrew Waterman
ec0d178010 Support M-mode-only implementations 2016-05-25 15:40:53 -07:00
Andrew Waterman
00ea9a7d82 Remove most of mstatus when user mode isn't supported 2016-05-25 15:37:32 -07:00
Andrew Waterman
5442b89664 Remove unnecessary muxes in RV32 MulDiv 2016-05-25 14:27:02 -07:00
Andrew Waterman
9aa724706e Don't include RV64 instructions in RV32 decode table 2016-05-25 14:26:45 -07:00
Wesley W. Terpstra
7f1792cba3 ahb: backport bridge to chisel2 
Closes #47
 2016-05-25 13:40:24 -07:00
Andrew Waterman
da105a5944 Don't allow travis to recurse through submodules 2016-05-25 13:27:49 -07:00
Wesley W. Terpstra
1c8745dfd2 ahb: backport to chisel2 
Merges #16
 2016-05-25 12:11:26 -07:00
Wesley W. Terpstra
da566e7d6a build: use local sbt when building firrtl 2016-05-25 11:48:03 -07:00
Andrew Waterman
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Andrew Waterman
a8462d3cfc bump chisel 2016-05-25 11:09:50 -07:00
Matthew Naylor
213bb26367 Drive invalidate_lr signal 
The DCache input for invalidating LR reservations was dangling.  Now
we wire it to false.
 2016-05-25 13:27:12 +01:00
Donggyu
a9599302bd fix cloneType in nasti.scala (#14) 2016-05-24 17:10:17 -07:00
Andrew Waterman
5bc78aba99 Merge pull request #15 from terpstra/ahb 
Ahb
 2016-05-24 17:06:03 -07:00
Andrew Waterman
c49cb10c74 Merge pull request #42 from terpstra/ahb 
Ahb
 2016-05-24 17:02:15 -07:00
Andrew Waterman
4605b616c1 Fix bug in D$ AMO/storegen logic 2016-05-24 16:26:07 -07:00
Andrew Waterman
88cc91db75 Ignore way_en in MetadataArray for direct-mapped caches 2016-05-24 15:47:09 -07:00
Andrew Waterman
5dac7b818d Support set associativity in blocking D$ 2016-05-24 15:45:52 -07:00
Andrew Waterman
e0addb5723 Support uncached AMOs in blocking D$ 2016-05-24 15:45:35 -07:00
Andrew Waterman
f14d87e327 Support larger I$ sets when VM is disabled 2016-05-24 15:44:59 -07:00
Andrew Waterman
3b35c7470e Add uncached support to blocking D$ 2016-05-24 15:05:41 -07:00
Andrew Waterman
42f079ce57 JAL requires DW_XPR 
This has been benign so far because of how the logic minimization worked.
 2016-05-24 15:05:41 -07:00
Andrew Waterman
b92c73e361 Add LR/SC to blocking D$ 2016-05-24 15:05:41 -07:00
Andrew Waterman
0d93d1a1a0 Clean up pending store logic a bit 2016-05-24 15:05:41 -07:00
Andrew Waterman
0b8de578d4 Add additional D$ store buffering to prevent structural hazards 2016-05-24 15:05:41 -07:00
Andrew Waterman
354cb2d5ec Don't stall I$ response when resolving a branch misprediction 
This avoids a fetch bubble.

Not clear if this is the best way to do it.  Perhaps this change should
instead be made to Frontend (i.e., ignore resp.ready when req.valid is
high), but that might exacerbate a critical path.
 2016-05-24 15:05:41 -07:00
Andrew Waterman
d7790ac6a4 WIP on blocking D$ 2016-05-24 15:05:41 -07:00
Andrew Waterman
335e2c8a1e Support disabling atomics extension 2016-05-24 15:05:41 -07:00
Andrew Waterman
765b90f6a4 Stall on D$ lockups less conservatively 2016-05-24 15:05:41 -07:00
Andrew Waterman
a3061047e3 Instantiate blocking D$ when NMSHRS=0 2016-05-24 15:05:41 -07:00
Andrew Waterman
80482890fd Don't rely on tag value for nacks 2016-05-24 15:05:41 -07:00
Wesley W. Terpstra
e19c5e5d2c IOMSHR: support atomic operations 2016-05-24 15:00:50 -07:00
Wesley W. Terpstra
a012341d96 ahb: TileLink => AHB bridge, including atomics and bursts 2016-05-24 14:58:27 -07:00
Wesley W. Terpstra
ace9362d81 ahb: amoalu does not need so many parameters! (i want to reuse it) 2016-05-24 14:58:27 -07:00
Wesley W. Terpstra
b921bae107 ahb: eliminate trait abused for constants 2016-05-24 14:20:45 -07:00
Wesley W. Terpstra
200c69c106 ahb: support hmastlock acquistion of crossbar 2016-05-24 14:20:45 -07:00
Wesley W. Terpstra
e1e8eda419 ahb: add a test SRAM 2016-05-24 14:20:42 -07:00
Wesley W. Terpstra
1db40687c6 ahb: eliminate now-unnecesary non-standard hreadyin 2016-05-24 14:14:22 -07:00
Wesley W. Terpstra
15cad8414d ahb: put signals in the order they appear in signal traces in the spec 2016-05-24 14:14:22 -07:00
Wesley W. Terpstra
f30f8d9f79 ahb: reduce obsolete degenerate cases of a crossbar 2016-05-24 14:14:22 -07:00
Wesley W. Terpstra
0368b6db6b ahb: replace defective crossbar with a functional one 
The previous crossbar had the following bugs:
  1. a bursting master could be preempted
     the AHB-lite spec requires a slave receive the entire burst

  2. a waited master could be replaced
     the AHB-lite spec requires haddr/etc to remain unchanged

  3. hmastlock did no ensure exclusive access
     atomic operations could be pre-empted
 2016-05-24 14:14:22 -07:00
Wesley W. Terpstra
2b37f37335 ahb: helper methods 2016-05-24 14:14:21 -07:00
Wesley W. Terpstra
ef2aae26a8 ahb: rename hreadyout to standard hready, mark hreadyin for death 2016-05-24 14:14:21 -07:00
Wesley W. Terpstra
2f8a77f27a ahb: include all AHB-lite constants 2016-05-24 14:14:21 -07:00
Wesley W. Terpstra
7896c4157e ahb: parameterize poci 2016-05-24 14:14:21 -07:00
Wesley W. Terpstra
93447eb274 ahb: make hasti parameters location sensitive 2016-05-24 14:14:17 -07:00
Wesley W. Terpstra
00d31dc5c5 bram: use new hasti definitions 2016-05-24 13:35:16 -07:00