Adam Izraelevitz
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812353bace
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Ported FPU parameters to new Chisel Parameters
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2014-08-19 11:37:27 -07:00 |
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Andrew Waterman
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04593d433e
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clean up Int <-> Boolean conversion stuff
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2014-06-14 13:58:07 -07:00 |
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Henry Cook
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1b156c6db9
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TileLinkIO.GrantAck -> TileLinkIO.Finish
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2014-04-26 15:18:21 -07:00 |
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Henry Cook
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910b3b203a
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removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
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2014-04-10 12:32:44 -07:00 |
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Henry Cook
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ebdc0a2692
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merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
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2014-04-10 12:09:52 -07:00 |
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Andrew Waterman
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c7110c8389
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Make FPU pipeline depths configurable
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2014-02-28 13:39:59 -08:00 |
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Yunsup Lee
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97b1841fcf
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change dcache tag bits to 7
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2014-02-22 22:53:04 -08:00 |
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Stephen Twigg
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6a02d15c21
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Merge branch 'master' into hwacha-port
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2014-02-04 17:05:03 -08:00 |
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Henry Cook
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2c2b3a7678
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cleanups supporting uncore hierarchy
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2014-01-31 12:07:26 -08:00 |
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Andrew Waterman
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0266c1f76a
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Support retirement width > 1 in CSR file
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2014-01-24 16:37:40 -08:00 |
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Yunsup Lee
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6bbbf36979
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push accel/rocket dmem port back to rocket
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2014-01-16 16:01:41 -08:00 |
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Quan Nguyen
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ebec444ad2
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Increase tag width for configurable precision in Hwacha
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2013-12-13 03:33:02 -08:00 |
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Yunsup Lee
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4c56323f6f
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hookup all memory ports
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2013-11-05 17:12:09 -08:00 |
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Stephen Twigg
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eae571e371
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Remove rocc memory simplifye module (Hwacha has its own)
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2013-11-05 15:31:03 -08:00 |
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Stephen Twigg
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36b85b8ee2
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Fix issue where the MSB of D$ req tag was getting lost for all agents when an accelerator was attached.
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2013-09-25 11:51:10 -07:00 |
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Andrew Waterman
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81c752de84
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Support disabling virtual memory
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2013-09-24 13:58:47 -07:00 |
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Andrew Waterman
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f12bbc1e43
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working RoCC AccumulatorExample
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2013-09-14 22:34:53 -07:00 |
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Andrew Waterman
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d053bdc89f
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Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
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2013-09-12 22:34:38 -07:00 |
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Andrew Waterman
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d4a0db4575
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Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
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Henry Cook
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ae02ebd153
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Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
Conflicts:
src/core.scala
src/ctrl.scala
src/dpath_util.scala
src/fpu.scala
src/nbdcache.scala
src/tile.scala
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2013-08-15 16:35:27 -07:00 |
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Henry Cook
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b570435847
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Reg standardization
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2013-08-13 17:50:02 -07:00 |
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Henry Cook
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858169917e
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removed dummy DNCs handled by pruning
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2013-08-12 22:34:46 -07:00 |
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Huy Vo
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387cf0ebe0
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reset -> resetVal, getReset -> reset
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2013-08-12 20:51:54 -07:00 |
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Henry Cook
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
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Henry Cook
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4eaab214d2
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:29:51 -07:00 |
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Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
|
Henry Cook
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5c00d0a030
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new tilelink arbiter type
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2013-07-09 15:31:46 -07:00 |
|
Henry Cook
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69b508ff39
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ported caches and htif to use new tilelink
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2013-05-21 17:21:04 -07:00 |
|
Henry Cook
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16113a96ba
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fixes after merge
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2013-03-25 19:09:08 -07:00 |
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Henry Cook
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95f0a688e9
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Merge branch 'release-xacts'
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
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2013-03-20 17:37:50 -07:00 |
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Henry Cook
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273bd34091
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Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
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2013-03-20 15:53:36 -07:00 |
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Henry Cook
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6d2541aced
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nTiles -> nClients in LogicalNetworkConfig
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2013-03-20 14:12:36 -07:00 |
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Andrew Waterman
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ea9d0b771e
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remove aborts; simplify probes
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2013-03-19 15:29:40 -07:00 |
|
Henry Cook
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e0361840bd
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writebacks on release network pass asm tests and bmarks
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2013-02-28 18:11:40 -08:00 |
|
Henry Cook
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931cffa749
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ready signal fix
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2013-01-27 23:04:35 -08:00 |
|
Henry Cook
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409b549d3c
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actually cleared up tile ios
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2013-01-27 11:27:09 -08:00 |
|
Henry Cook
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696dd102eb
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cleans up unconnected tile io pins (networking headers overwritten at top level)
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2013-01-27 10:59:41 -08:00 |
|
Henry Cook
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6b00e7ff74
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New TileLink bundle names
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2013-01-21 17:18:23 -08:00 |
|
Henry Cook
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a2fa3fd04d
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Refactored packet headers/payloads
|
2013-01-15 15:50:37 -08:00 |
|
Henry Cook
|
e1225c5114
|
standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
|
Henry Cook
|
261e14f831
|
Refactored uncore conf
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2013-01-07 13:41:36 -08:00 |
|
Andrew Waterman
|
78868f6075
|
add config option to trade mul/div area for speed
|
2013-01-06 03:47:17 -08:00 |
|
Andrew Waterman
|
c036cdc1ea
|
add option for 2-cycle load-use delay
|
2012-11-24 22:01:08 -08:00 |
|
Andrew Waterman
|
29bc361d6c
|
remove global constants; disentangle hwacha a bit
|
2012-11-17 17:24:08 -08:00 |
|
Andrew Waterman
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8dce89703a
|
new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
|
2012-11-16 02:39:33 -08:00 |
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Andrew Waterman
|
4d1ca8ba3a
|
remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
|
2012-11-06 08:13:44 -08:00 |
|
Andrew Waterman
|
c5b93798fb
|
factor out more global constants
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2012-11-05 23:52:32 -08:00 |
|
Andrew Waterman
|
e9eca6a95d
|
refactor I$ config; remove Top class
|
2012-11-04 16:59:36 -08:00 |
|
Andrew Waterman
|
7380c9fe60
|
aggressively clock gate int and fp datapaths
|
2012-11-04 16:40:14 -08:00 |
|
Andrew Waterman
|
5773cbb68a
|
rejigger htif to use UncoreConfiguration
|
2012-10-18 17:26:03 -07:00 |
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