riscv/rocket-chip
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Author SHA1 Message Date
Wesley W. TerpstraandGitHub 48ca478578 Merge branch 'master' into intbar 2016-09-08 21:09:59 -07:00
Wesley W. TerpstraandGitHub 808a7f60f4 tilelink2 Legacy: it's only an error if it's valid (#264) 2016-09-08 21:09:40 -07:00
Wesley W. Terpstra 1b07d53f70 tilelink2 IntNodes: record interrupt ranges in parameters 2016-09-08 18:51:43 -07:00
Wesley W. Terpstra 66f58cf2d0 tilelink2 RegisterRouter: support new TL2 interrupts 2016-09-08 15:25:50 -07:00
Wesley W. Terpstra 23e896ed5d tilelink2 IntNodes: support interrupt graphs 2016-09-08 15:25:48 -07:00
Wesley W. Terpstra d7df7d3109 tilelink2: connect Nodes to LazyModules for better error messages 2016-09-08 15:24:04 -07:00
Wesley W. Terpstra 53987cd9d4 tilelink2 Nodes: support non-Bundle data for io type 2016-09-08 15:19:12 -07:00
Wesley W. Terpstra 60a503dc2f tilelink2 RegField: add a w1ToClear RegField 2016-09-08 14:02:49 -07:00
Wesley W. Terpstra 99b7e734cd tilelink2 Bundles: fix wrong sink width! 2016-09-08 13:47:40 -07:00
Wesley W. TerpstraandHenry Cook 9bfd8c1cf5 TL2 WidthWidget (#258) 
* tilelink2 Narrower: support widenening and narrowing on all channels

Be extra careful with the mask transformations

We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.

* tilelink2 SRAM: work around firrtl SeqMem bug

* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)

* tilelink2 mask: fix an issue with width=1 data buses
 2016-09-08 10:38:38 -07:00
Wesley W. Terpstra d2421654c4 tilelink2: refactor address into addr_hi on ABC and addr_lo on CD 
We need addr_lo in order to properly convert widths.
As part of the refactoring, move all methods out of the Bundles
 2016-09-06 23:46:44 -07:00
Wesley W. Terpstra aae4230627 tilelink2: fix bugs found by Megan in Legacy converter 2016-09-06 13:12:33 -07:00
Wesley W. Terpstra 54ab14cd9d tilelink2: statically optimize numBeats for simple managers 2016-09-05 22:11:03 -07:00
Wesley W. Terpstra 314d6ebd6f tilelink2: stricter TransferSizes requirements 2016-09-05 22:10:28 -07:00
Wesley W. Terpstra 56170c605c tilelink2: be more forgiving in what Legacy TL requires 2016-09-05 21:12:51 -07:00
Wesley W. Terpstra 3167539331 tilelink2: Narrower must be little-endian 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra ded246fb95 tilelink2: relax max transfer size; the real requirement is not exceeding alignment 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra cf0291061d tilelink2: fix a bug in UIntToOH1 triggered if the size was too big 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 9f45212c95 tilelink2: Fragmenter needs to update subaddress 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 757d46279e tilelink2: expand data correctly in D channel narrower 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 0faa8c4051 tilelink2: fix Xbar bug where Mux1H broke FSM if only one manager 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra a0c25880c7 tilelink2: Monitor should check mask of reconstructed request 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra df32cc3887 tilelink2: be careful; apply Andrew's masking trick everywhere 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra fb262558ee tilelink2: helper objects should pass source line from where they were invoked 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 1a081b4dd5 tilelink2: Monitor should report which TL connection was the problem 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra cb54df0a8a tilelink2: tie off unused channels 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra 68e64a9859 tilelink2: clarify ready-valid use of RegisterRouter 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra e3b3543841 tilelink2: ensure RegFields don't exceed their bounds 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 8343070639 tilelink2: detect 1-bit overflow in register definitions 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra a1fc01fd6d tilelink2: prevent mapping the same register twice 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 81162a2dc9 tilelink2: support attaching a DecoupledIO directly to a register 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 6a378e79e3 tilelink2: allow 0-stage backpressure in combinational regmap 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 4746cf00ce tilelink2: move files to new uncore directory 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra e034775bfa tilelink2: use the fancy new hasData functions 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 11b0272d91 tilelink2: create optimized hasData method on edges (statically evaluates if known) 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 5db7ae262b tilelink2: first version of Narrower (only supports uncached IO) 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra b004d54d71 tilelink2: add a Fragmenter adapter 
God that was a pain in the ass!
 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra ecc3c2a4b2 tilelink2: more efficient one-hot circuits 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 3d84795641 tilelink2: use LazyModule(new ...) just like Chisel Module(new ...) 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 2069ca5d8d tilelink2: pass sourceInfo using implicits in Monitor 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 935b53f3bf tilelink2: explicitly check that fixed fields never change in multibeat 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra e652cd155b tilelink2: edge parameters on the same link had better match 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra c411a3e77f tilelink2: simpler sizes requirement for users to understand 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra ab998c08f1 tilelink2: save some hardware in HintHandler if no BCE 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 18e7d4cd65 tilelink2: make it possible to write Node-only adapters 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra 4a401fc480 tilelink2: add a Buffer adapter to insert pipeline stages 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra 50f0dee69e tilelink2: add an IdentityNode for adapters that change nothing 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra 9cd2991fb3 tilelink2: AddressSet always has an assigned base address 
The consensus seems to be that TileLink should not be assigning
addresses dynamically. The reasons:

1. We can come up with another scheme for assigning addresses that is
   independent of TileLink.  This decoupling is good, because it would
   allow us to use the same mechanism for different buses in the SoC.

2. The informational flow of addresses is more likely to naturally follow
   the module hierarchy than the TileLike bus topology. Thus, it seems
   better to pass address parameterization using Module constructors.

3. Addresses are still checked by TileLink, so using a Module-centric
   flow for addresses will not pose a correctness concern.

4. An address need only be provided to a slave on its construction and
   TileLink parameterization spreads this globally. Thus, the burden to
   manually assign an address is low.
 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra ae2bc4da21 tilelink2: refactor RegField into interface and implementation 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra d6727abbbc tilelink2: rename Operations to Edges (as it only includes Edges) 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra ee3e31cb23 tilelink2: refactor TLNodes into a seperate file 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra 69b3de92a8 tilelink2: decouple BaseNode from TileLink bus (so it can be reused) 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra c785375276 tilelink2: use 'connect' instead of TL-specific 'tl' to connect nodes 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra 05221d7073 tilelink2: rename Bases.scala to LazyModule.scala 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra 8d54ae8508 tilelink2: move TL-specific stuff out of the LazyModule base classes 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra f99a3dbec7 tilelink2: rename Factory=>LazyModule and TLModule=>LazyModuleImp 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra 5b31fb81fe tilelink2: IDNode needs to be specialized for output vs. input passthrough 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra eac4d44131 tilelink2: don't apply HintHandler to B=>C by default 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra cc8112d02e tilelink2: pass E through the HintHandler 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra a72f7115ae tilelink2: optimize support testing circuits 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra f0cfd81820 tilelink2: add an adapter to add support for Hints to devices 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra 5f6ca0bd0d tilelink2: rename wmask => mask since it also applies to reads 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra 7347b0c4dd tilelink2: TLLegacy converts from legacy TileLink to TileLink2 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra fa472e38fb tilelink2: monitor error line legality 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra edb17d1e34 tilelink2: document allowed (and required) response messages 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra ec1f901a38 tilelink2: move error from type into Bundle and add HintAck 
We need Grant with errors too.
We also want to match response type to request type more easily.
 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 534d7f6eb6 tilelink2: implement SRAM manager 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 32894a8e20 tilelink2: transfers must never exceed 4kB 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra dd27a60daa tilelink2: use consistent in/out ports for TLSimpleFactories 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 1a87eef3e2 tilelink2: add atomic message types 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 5f7711a0c0 tilelink2: add an intermediate type for simple factories 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 967d8f108c tilelink2: support ready-valid enqueue+dequeue on register fields 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 77cf186cf0 tilelink2: make bundle parameterization reusable 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 594850eaae tilelink2: assert-fail on something more user understandable 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra dc1164a996 tilelink2: defer bundle construction until after Module base class instantiated 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 18e149098a tilelink2: connect abstract register-based modules to TileLink 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 917a9c8e5d tilelink2: forward declarations for message constructors 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 4649c42f50 tilelink2: use a new type in the signature of null-parameter Bundle methods 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 0ff33a31a4 tilelink2: add a stub SRAM manager 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra a87c2d13e2 tilelink2: include an abstract definition for register mapped devices 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 3a441d853f tilelink2: clarify that fifoId only applies to accesses (not hints) 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 4b99bd3be1 tilelink2: mask out unnecessary address bits 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra e24ba61754 tilelink2: distinguish two levels of uncacheability 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra e506309998 tilelink2: prototype crossbar implementation 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 34f65938b6 tilelink2: add a TLBundle constructor 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 1cd85ff050 tilelink2: add some bundle introspection to scaffold the xbar 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 9c62f5d9c1 tilelink2: shave off a few more firrtl monitor lines 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra af29595979 tilelink2: eliminate common subexpressions in Monitor to reduce firrtl output 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra d7e839280f tilelink2: include legal message monitor 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 492a38aedc tilelink2: only accesses can have errors (release must make forward progress) 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 6599bcb77b tilelink2: statically check Operations are remotely plausible 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 8cff45f254 tilelink2: use byte-aligned addressing 
This makes it possible to fully validate user input in a monitor.
We will override the lower bits with constant 0s in the TL connect.
 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 45e152e97e tilelink2: include Operation constructors 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 5b10c1a328 tilelink2: arithmetic and logical atomics must be distinct (priv spec 3.5.3) 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 8592cbf0e3 tilelink2: Message and Permisison types from Henry 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 9a460322da tilelink2: add synthesizable test methods for Parameters 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 7328b55abd tilelink2: first cut at parameterization 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 11ec5b2cf4 bram: don't deal with multibeat; rely on the fragmenter 2016-07-22 14:51:05 -07:00
Wesley W. TerpstraandHoward Mao a52d418439 fragmenter: support multi-beat get/put via fragmenting to single-beat operations 2016-07-22 14:48:22 -07:00
Wesley W. TerpstraandHoward Mao 9ae23f18bd rocket: support asynchronous external busses 2016-07-19 14:52:56 -07:00