TL2 WidthWidget (#258)
* tilelink2 Narrower: support widenening and narrowing on all channels Be extra careful with the mask transformations We need to make sure that narrowing or widening do not cause a loss of information about the operation. The addr_hi+(mask|addr_lo) conversions are now 1-1, except on D, which should not matter. * tilelink2 SRAM: work around firrtl SeqMem bug * tilelink2 WidthWidget: renamed from Narrower (it now converts both ways) * tilelink2 mask: fix an issue with width=1 data buses
This commit is contained in:
Wesley W. Terpstra
Henry Cook
parent
8536a2a47d
commit
9bfd8c1cf5
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@ -100,7 +100,7 @@ object TLAtomics
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def isLogical(x: UInt) = x <= SWAP
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}
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sealed trait TLChannel
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sealed trait TLChannel extends TLBundleBase
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sealed trait TLDataChannel extends TLChannel
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sealed trait TLAddrChannel extends TLDataChannel
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@ -27,7 +27,7 @@ class TLEdge(
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// This gets used everywhere, so make the smallest circuit possible ...
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def mask(addr_lo: UInt, lgSize: UInt): UInt = {
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val lgBytes = log2Ceil(manager.beatBytes)
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val sizeOH = UIntToOH(lgSize, lgBytes)
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val sizeOH = UIntToOH(lgSize, log2Up(manager.beatBytes))
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def helper(i: Int): Seq[(Bool, Bool)] = {
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if (i == 0) {
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Seq((lgSize >= UInt(lgBytes), Bool(true)))
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@ -1,138 +0,0 @@
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import scala.math.{min,max}
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// innBeatBytes => the bus width after the adapter
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class TLNarrower(innerBeatBytes: Int) extends LazyModule
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{
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val node = TLAdapterNode(
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clientFn = { case Seq(c) => c },
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managerFn = { case Seq(m) => m.copy(beatBytes = innerBeatBytes) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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val edgeOut = node.edgesOut(0)
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val edgeIn = node.edgesIn(0)
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val outerBeatBytes = edgeOut.manager.beatBytes
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require (outerBeatBytes < innerBeatBytes)
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val ratio = innerBeatBytes / outerBeatBytes
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val bce = edgeOut.manager.anySupportAcquire && edgeIn.client.anySupportProbe
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def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
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def split(edge: TLEdge, in: TLDataChannel, fire: Bool): (Bool, UInt, UInt) = {
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val dataSlices = Vec.tabulate (ratio) { i => edge.data(in)((i+1)*outerBeatBytes*8-1, i*outerBeatBytes*8) }
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val maskSlices = Vec.tabulate (ratio) { i => edge.mask(in)((i+1)*outerBeatBytes -1, i*outerBeatBytes) }
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val filter = Reg(UInt(width = ratio), init = SInt(-1, width = ratio).asUInt)
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val mask = maskSlices.map(_.orR)
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val hasData = edge.hasData(in)
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// decoded_size = 1111 (for smallest), 0101, 0001 (for largest)
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val sizeOH1 = UIntToOH1(edge.size(in), log2Ceil(innerBeatBytes)) >> log2Ceil(outerBeatBytes)
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val decoded_size = Seq.tabulate(ratio) { i => trailingZeros(i).map(!sizeOH1(_)).getOrElse(Bool(true)) }
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val first = filter(ratio-1)
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val new_filter = Mux(first, Cat(decoded_size.reverse), filter << 1)
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val last = new_filter(ratio-1) || !hasData
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when (fire) {
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filter := new_filter
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when (!hasData) { filter := SInt(-1, width = ratio).asUInt }
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}
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if (edge.staticHasData(in) == Some(false)) {
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(Bool(true), UInt(0), UInt(0))
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} else {
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val select = Cat(mask.reverse) & new_filter
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(last, Mux1H(select, dataSlices), Mux1H(select, maskSlices))
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}
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}
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def merge(edge: TLEdge, in: TLDataChannel, fire: Bool): (Bool, UInt) = {
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val count = RegInit(UInt(0, width = log2Ceil(ratio)))
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val rdata = Reg(UInt(width = (ratio-1)*outerBeatBytes*8))
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val data = Cat(edge.data(in), rdata)
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val first = count === UInt(0)
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val limit = UIntToOH1(edge.size(in), log2Ceil(innerBeatBytes)) >> log2Ceil(outerBeatBytes)
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val last = count === limit || !edge.hasData(in)
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when (fire) {
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rdata := data >> outerBeatBytes*8
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count := count + UInt(1)
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when (last) { count := UInt(0) }
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}
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val cases = Seq.tabulate(log2Ceil(ratio)+1) { i =>
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val high = innerBeatBytes*8
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val take = (1 << i)*outerBeatBytes*8
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Fill(1 << (log2Ceil(ratio)-i), data(high-1, high-take))
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}
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val mux = Vec.tabulate(log2Ceil(edge.maxTransfer)+1) { lgSize =>
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cases(min(max(lgSize - log2Ceil(outerBeatBytes), 0), log2Ceil(ratio)))
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}
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if (edge.staticHasData(in) == Some(false)) {
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(Bool(true), UInt(0))
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} else {
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(last, mux(edge.size(in)))
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}
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}
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val in = io.in(0)
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val out = io.out(0)
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val (alast, adata, amask) = split(edgeIn, in.a.bits, out.a.fire())
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in.a.ready := out.a.ready && alast
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out.a.valid := in.a.valid
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out.a.bits := in.a.bits
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out.a.bits.addr_hi := Cat(in.a.bits.addr_hi, edgeIn.addr_lo(in.a.bits) >> log2Ceil(outerBeatBytes))
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out.a.bits.data := adata
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out.a.bits.mask := amask
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val (dlast, ddata) = merge(edgeOut, out.d.bits, out.d.fire())
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out.d.ready := in.d.ready || !dlast
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in.d.valid := out.d.valid && dlast
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in.d.bits := out.d.bits
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in.d.bits.data := ddata
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if (bce) {
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require (false)
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// C has no wmask !!!
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// val (clast, cdata, cmask) = split(in.c.bits, out.c.fire())
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// in.c.ready := out.c.ready && clast
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// out.c.valid := in.c.valid
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// out.c.bits := in.c.bits
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// out.c.bits.data := cdata
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// out.c.bits.mask := cmask
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in.e.ready := out.e.ready
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out.e.valid := in.e.valid
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out.e.bits := in.e.bits
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} else {
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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}
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}
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}
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object TLNarrower
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{
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// applied to the TL source node; connect (Narrower(x.node, 16) -> y.node)
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def apply(x: TLBaseNode, innerBeatBytes: Int)(implicit lazyModule: LazyModule, sourceInfo: SourceInfo): TLBaseNode = {
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val narrower = LazyModule(new TLNarrower(innerBeatBytes))
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lazyModule.connect(x -> narrower.node)
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narrower.node
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}
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}
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@ -59,13 +59,14 @@ class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule
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d_size := in.a.bits.size
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d_source := in.a.bits.source
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d_addr := edge.addr_lo(in.a.bits)
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when (read) {
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rdata := mem.read(memAddress)
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} .otherwise {
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mem.write(memAddress, wdata, in.a.bits.mask.toBools)
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}
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}
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// exactly this pattern is required to get a RWM memory
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when (in.a.fire() && !read) {
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mem.write(memAddress, wdata, in.a.bits.mask.toBools)
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}
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rdata := mem.read(memAddress, in.a.fire() && read)
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// Tie off unused channels
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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@ -0,0 +1,180 @@
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import scala.math.{min,max}
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// innBeatBytes => the new client-facing bus width
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class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
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{
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val node = TLAdapterNode(
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clientFn = { case Seq(c) => c },
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managerFn = { case Seq(m) => m.copy(beatBytes = innerBeatBytes) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
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val inBytes = edgeIn.manager.beatBytes
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val outBytes = edgeOut.manager.beatBytes
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val ratio = outBytes / inBytes
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val rdata = Reg(UInt(width = (ratio-1)*inBytes*8))
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val rmask = Reg(UInt(width = (ratio-1)*inBytes))
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val data = Cat(edgeIn.data(in.bits), rdata)
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val mask = Cat(edgeIn.mask(in.bits), rmask)
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val size = edgeIn.size(in.bits)
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val hasData = edgeIn.hasData(in.bits)
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val addr_lo = in.bits match {
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case x: TLAddrChannel => edgeIn.address(x)
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case _ => UInt(0)
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}
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val addr = addr_lo >> log2Ceil(outBytes)
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val count = RegInit(UInt(0, width = log2Ceil(ratio)))
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val first = count === UInt(0)
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val limit = UIntToOH1(size, log2Ceil(outBytes)) >> log2Ceil(inBytes)
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val last = count === limit || !hasData
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when (in.fire()) {
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rdata := data >> inBytes*8
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rmask := mask >> inBytes
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count := count + UInt(1)
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when (last) { count := UInt(0) }
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}
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val cases = Seq.tabulate(log2Ceil(ratio)+1) { i =>
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val high = outBytes
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val take = (1 << i)*inBytes
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(Fill(1 << (log2Ceil(ratio)-i), data(high*8-1, (high-take)*8)),
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Fill(1 << (log2Ceil(ratio)-i), mask(high -1, (high-take))))
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}
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val dataMux = Vec.tabulate(log2Ceil(edgeIn.maxTransfer)+1) { lgSize =>
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cases(min(max(lgSize - log2Ceil(inBytes), 0), log2Ceil(ratio)))._1
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}
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val maskMux = Vec.tabulate(log2Ceil(edgeIn.maxTransfer)+1) { lgSize =>
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cases(min(max(lgSize - log2Ceil(inBytes), 0), log2Ceil(ratio)))._2
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}
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val dataOut = if (edgeIn.staticHasData(in.bits) == Some(false)) UInt(0) else dataMux(size)
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val maskOut = maskMux(size) & edgeOut.mask(addr_lo, size)
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in.ready := out.ready || !last
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out.valid := in.valid && last
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out.bits := in.bits
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edgeOut.data(out.bits) := dataOut
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out.bits match {
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case a: TLBundleA => a.addr_hi := addr; a.mask := maskOut
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case b: TLBundleB => b.addr_hi := addr; b.mask := maskOut
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case c: TLBundleC => c.addr_hi := addr; c.addr_lo := addr_lo
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case d: TLBundleD => ()
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// addr_lo gets padded with 0s on D channel, the only lossy transform in this core
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// this should be safe, because we only care about addr_log on D to determine which
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// piece of data to extract when the D data bus is narrowed. Since we duplicated the
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// data to all locations, addr_lo still points at a valid copy.
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}
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}
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def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
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val inBytes = edgeIn.manager.beatBytes
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val outBytes = edgeOut.manager.beatBytes
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val ratio = inBytes / outBytes
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val hasData = edgeIn.hasData(in.bits)
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val size = edgeIn.size(in.bits)
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val data = edgeIn.data(in.bits)
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val mask = edgeIn.mask(in.bits)
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val addr = in.bits match {
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case x: TLAddrChannel => edgeIn.address(x) >> log2Ceil(outBytes)
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case _ => UInt(0)
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}
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val dataSlices = Vec.tabulate(ratio) { i => data((i+1)*outBytes*8-1, i*outBytes*8) }
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val maskSlices = Vec.tabulate(ratio) { i => mask((i+1)*outBytes -1, i*outBytes) }
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val filter = Reg(UInt(width = ratio), init = SInt(-1, width = ratio).asUInt)
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val maskR = maskSlices.map(_.orR)
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// decoded_size = 1111 (for smallest), 0101, 0001 (for largest)
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val sizeOH1 = UIntToOH1(size, log2Ceil(inBytes)) >> log2Ceil(outBytes)
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val decoded_size = Seq.tabulate(ratio) { i => trailingZeros(i).map(!sizeOH1(_)).getOrElse(Bool(true)) }
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val first = filter(ratio-1)
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val new_filter = Mux(first, Cat(decoded_size.reverse), filter << 1)
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val last = new_filter(ratio-1) || !hasData
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when (out.fire()) {
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filter := new_filter
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when (!hasData) { filter := SInt(-1, width = ratio).asUInt }
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}
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val select = Cat(maskR.reverse) & new_filter
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val dataOut = if (edgeIn.staticHasData(in.bits) == Some(false)) UInt(0) else Mux1H(select, dataSlices)
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val maskOut = Mux1H(select, maskSlices)
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in.ready := out.ready && last
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out.valid := in.valid
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out.bits := in.bits
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edgeOut.data(out.bits) := dataOut
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out.bits match {
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case a: TLBundleA => a.addr_hi := addr; a.mask := maskOut
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case b: TLBundleB => b.addr_hi := addr; b.mask := maskOut
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case c: TLBundleC => c.addr_hi := addr
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case d: TLBundleD => ()
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}
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// addr_lo gets truncated automagically
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}
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def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
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if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
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// nothing to do; pass it through
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out <> in
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} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
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// split input to output
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split(edgeIn, in, edgeOut, out)
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} else {
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// merge input to output
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merge(edgeIn, in, edgeOut, out)
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}
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}
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val edgeOut = node.edgesOut(0)
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val edgeIn = node.edgesIn(0)
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val in = io.in(0)
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val out = io.out(0)
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splice(edgeIn, in.a, edgeOut, out.a)
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splice(edgeOut, out.d, edgeIn, in.d)
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if (edgeOut.manager.anySupportAcquire && edgeIn.client.anySupportProbe) {
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splice(edgeOut, out.b, edgeIn, in.b)
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splice(edgeIn, in.c, edgeOut, out.c)
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in.e.ready := out.e.ready
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out.e.valid := in.e.valid
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out.e.bits := in.e.bits
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} else {
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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}
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}
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}
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object TLWidthWidget
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{
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// applied to the TL source node; connect (WidthWidget(x.node, 16) -> y.node)
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def apply(x: TLBaseNode, innerBeatBytes: Int)(implicit lazyModule: LazyModule, sourceInfo: SourceInfo): TLBaseNode = {
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val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
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lazyModule.connect(x -> widget.node)
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widget.node
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}
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}
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@ -7,4 +7,5 @@ package object tilelink2
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type TLBaseNode = BaseNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
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def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x)
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def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
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def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
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}
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