tilelink2: prevent mapping the same register twice

2016-09-02 22:41:42 -07:00 · 2016-09-02 22:41:42 -07:00 · a1fc01fd6d
commit a1fc01fd6d
parent 81162a2dc9
1 changed files with 5 additions and 0 deletions
--- a/src/main/scala/uncore/tilelink2/RegMapper.scala
+++ b/src/main/scala/uncore/tilelink2/RegMapper.scala
@ -31,6 +31,11 @@ object RegMapper
    val regmap = mapping.toList
    require (!regmap.isEmpty)

+    // Ensure no register appears twice
+    regmap.combinations(2).foreach { case Seq((reg1, _), (reg2, _)) =>
+      require (reg1 != reg2)
+    }
+
    // Flatten the regmap into (Reg:Int, Offset:Int, field:RegField)
    val flat = regmap.map { case (reg, fields) =>
      val offsets = fields.scanLeft(0)(_ + _.width).init