tilelink2: refactor TLNodes into a seperate file
This commit is contained in:
Wesley W. Terpstra
@@ -20,36 +20,36 @@ abstract class NodeImp[PO, PI, EO, EI, B <: Bundle]
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}
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class BaseNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(
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private val clientFn: Option[Seq[PO] => PO],
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private val managerFn: Option[Seq[PI] => PI],
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private val numClientPorts: Range.Inclusive,
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private val numManagerPorts: Range.Inclusive)
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private val oFn: Option[Seq[PO] => PO],
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private val iFn: Option[Seq[PI] => PI],
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private val numPO: Range.Inclusive,
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private val numPI: Range.Inclusive)
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{
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// At least 0 ports must be supported
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require (!numClientPorts.isEmpty)
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require (!numManagerPorts.isEmpty)
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require (numClientPorts.start >= 0)
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require (numManagerPorts.start >= 0)
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require (!numPO.isEmpty)
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require (!numPI.isEmpty)
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require (numPO.start >= 0)
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require (numPI.start >= 0)
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val noClients = numClientPorts.size == 1 && numClientPorts.contains(0)
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val noManagers = numManagerPorts.size == 1 && numManagerPorts.contains(0)
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val noOs = numPO.size == 1 && numPO.contains(0)
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val noIs = numPI.size == 1 && numPI.contains(0)
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require (noClients || clientFn.isDefined)
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require (noManagers || managerFn.isDefined)
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require (noOs || oFn.isDefined)
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require (noIs || iFn.isDefined)
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private val accClientPorts = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
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private val accManagerPorts = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
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private var clientRealized = false
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private var managerRealized = false
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private val accPO = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
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private val accPI = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
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private var oRealized = false
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private var iRealized = false
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private lazy val clientPorts = { clientRealized = true; require (numClientPorts.contains(accClientPorts.size)); accClientPorts.result() }
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private lazy val managerPorts = { managerRealized = true; require (numManagerPorts.contains(accManagerPorts.size)); accManagerPorts.result() }
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private lazy val clientParams : Option[PO] = clientFn.map(_(managerPorts.map(_.clientParams.get)))
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private lazy val managerParams : Option[PI] = managerFn.map(_(clientPorts.map(_.managerParams.get)))
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private lazy val oPorts = { oRealized = true; require (numPO.contains(accPO.size)); accPO.result() }
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private lazy val iPorts = { iRealized = true; require (numPI.contains(accPI.size)); accPI.result() }
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private lazy val oParams : Option[PO] = oFn.map(_(iPorts.map(_.oParams.get)))
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private lazy val iParams : Option[PI] = iFn.map(_(oPorts.map(_.iParams.get)))
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lazy val edgesOut = oPorts.map { n => imp.edgeO(oParams.get, n.iParams.get) }
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lazy val edgesIn = iPorts.map { n => imp.edgeI(n.oParams.get, iParams.get) }
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lazy val edgesOut = clientPorts.map { n => imp.edgeO(clientParams.get, n.managerParams.get) }
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lazy val edgesIn = managerPorts.map { n => imp.edgeI(n.clientParams.get, managerParams.get) }
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lazy val bundleOut = imp.bundleO(edgesOut)
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lazy val bundleIn = imp.bundleI(edgesIn)
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@@ -58,103 +58,50 @@ class BaseNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(
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// source.edge(sink)
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protected[tilelink2] def edge(x: BaseNode[PO, PI, EO, EI, B])(implicit sourceInfo: SourceInfo) = {
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require (!noClients)
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require (!clientRealized)
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require (!x.noManagers)
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require (!x.managerRealized)
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val i = x.accManagerPorts.size
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val o = accClientPorts.size
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accClientPorts += x
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x.accManagerPorts += this
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require (!noOs)
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require (!oRealized)
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require (!x.noIs)
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require (!x.iRealized)
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val i = x.accPI.size
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val o = accPO.size
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accPO += x
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x.accPI += this
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() => {
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imp.connect(connectOut(o), edgesOut(o), x.connectIn(i), x.edgesIn(i))
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}
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}
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}
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class TLClientNode(
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params: TLClientParameters,
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numPorts: Range.Inclusive = 1 to 1) extends BaseNode(TLImp)(
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clientFn = Some {case Seq() => TLClientPortParameters(Seq(params))},
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managerFn = None,
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numClientPorts = numPorts,
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numManagerPorts = 0 to 0)
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{
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require(numPorts.end >= 1)
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}
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object TLClientNode
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{
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def apply(
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params: TLClientParameters,
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numPorts: Range.Inclusive = 1 to 1) = new TLClientNode(params, numPorts)
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}
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class TLManagerNode(
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beatBytes: Int,
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params: TLManagerParameters,
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numPorts: Range.Inclusive = 1 to 1) extends BaseNode(TLImp)(
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clientFn = None,
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managerFn = Some {case Seq() => TLManagerPortParameters(Seq(params), beatBytes)},
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numClientPorts = 0 to 0,
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numManagerPorts = numPorts)
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{
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require(numPorts.end >= 1)
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}
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object TLManagerNode
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{
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def apply(
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beatBytes: Int,
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params: TLManagerParameters,
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numPorts: Range.Inclusive = 1 to 1) = new TLManagerNode(beatBytes, params, numPorts)
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}
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class TLAdapterNode(
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clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
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managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
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numClientPorts: Range.Inclusive = 1 to 1,
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numManagerPorts: Range.Inclusive = 1 to 1) extends BaseNode(TLImp)(
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clientFn = Some(clientFn),
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managerFn = Some(managerFn),
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numClientPorts = numClientPorts,
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numManagerPorts = numManagerPorts)
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object TLAdapterNode
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{
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def apply(
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clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
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managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
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numClientPorts: Range.Inclusive = 1 to 1,
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numManagerPorts: Range.Inclusive = 1 to 1) = new TLAdapterNode(clientFn, managerFn, numClientPorts, numManagerPorts)
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}
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class TLOutputNode extends BaseNode(TLImp)(
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clientFn = Some({case Seq(x) => x}),
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managerFn = Some({case Seq(x) => x}),
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numClientPorts = 1 to 1,
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numManagerPorts = 1 to 1)
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class OutputNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])
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extends BaseNode(imp)(Some{case Seq(x) => x}, Some{case Seq(x) => x}, 1 to 1, 1 to 1)
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{
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override def connectOut = bundleOut
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override def connectIn = bundleOut
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}
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object TLOutputNode
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{
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def apply() = new TLOutputNode()
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}
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class TLInputNode extends BaseNode(TLImp)(
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clientFn = Some({case Seq(x) => x}),
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managerFn = Some({case Seq(x) => x}),
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numClientPorts = 1 to 1,
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numManagerPorts = 1 to 1)
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class InputNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])
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extends BaseNode(imp)(Some{case Seq(x) => x}, Some{case Seq(x) => x}, 1 to 1, 1 to 1)
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{
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override def connectOut = bundleIn
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override def connectIn = bundleIn
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}
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object TLInputNode
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class SourceNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1)
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extends BaseNode(imp)(Some{case Seq() => po}, None, num, 0 to 0)
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{
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def apply() = new TLInputNode()
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require (num.end >= 1)
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}
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class SinkNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI, num: Range.Inclusive = 1 to 1)
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extends BaseNode(imp)(None, Some{case Seq() => pi}, 0 to 0, num)
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{
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require (num.end >= 1)
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}
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class InteriorNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])
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(oFn: Seq[PO] => PO, iFn: Seq[PI] => PI, numPO: Range.Inclusive, numPI: Range.Inclusive)
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extends BaseNode(imp)(Some(oFn), Some(iFn), numPO, numPI)
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{
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require (numPO.end >= 1)
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require (numPI.end >= 1)
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}
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@@ -431,26 +431,3 @@ class TLEdgeIn(
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d
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}
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}
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object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
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{
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def edgeO(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(po, pi)
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def edgeI(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(po, pi)
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def bundleO(eo: Seq[TLEdgeOut]): Vec[TLBundle] = {
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require (!eo.isEmpty)
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Vec(eo.size, TLBundle(eo.map(_.bundle).reduce(_.union(_))))
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}
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def bundleI(ei: Seq[TLEdgeIn]): Vec[TLBundle] = {
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require (!ei.isEmpty)
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Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip
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}
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def connect(bo: TLBundle, eo: TLEdgeOut, bi: TLBundle, ei: TLEdgeIn)(implicit sourceInfo: SourceInfo): Unit = {
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TLMonitor.legalize(bo, eo, bi, ei, sourceInfo)
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bi <> bo
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val mask = ~UInt(ei.manager.beatBytes - 1)
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bi.a.bits.address := (mask & bo.a.bits.address)
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bo.b.bits.address := (mask & bi.b.bits.address)
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bi.c.bits.address := (mask & bo.c.bits.address)
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}
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}
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46
uncore/src/main/scala/tilelink2/TLNodes.scala
Normal file
46
uncore/src/main/scala/tilelink2/TLNodes.scala
Normal file
@@ -0,0 +1,46 @@
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import scala.collection.mutable.ListBuffer
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import chisel3.internal.sourceinfo.SourceInfo
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object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
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{
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def edgeO(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(po, pi)
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def edgeI(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(po, pi)
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def bundleO(eo: Seq[TLEdgeOut]): Vec[TLBundle] = {
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require (!eo.isEmpty)
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Vec(eo.size, TLBundle(eo.map(_.bundle).reduce(_.union(_))))
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}
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def bundleI(ei: Seq[TLEdgeIn]): Vec[TLBundle] = {
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require (!ei.isEmpty)
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Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip
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}
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def connect(bo: TLBundle, eo: TLEdgeOut, bi: TLBundle, ei: TLEdgeIn)(implicit sourceInfo: SourceInfo): Unit = {
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TLMonitor.legalize(bo, eo, bi, ei, sourceInfo)
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bi <> bo
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val mask = ~UInt(ei.manager.beatBytes - 1)
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bi.a.bits.address := (mask & bo.a.bits.address)
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bo.b.bits.address := (mask & bi.b.bits.address)
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bi.c.bits.address := (mask & bo.c.bits.address)
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}
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}
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case class TLOutputNode() extends OutputNode(TLImp)
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case class TLInputNode() extends InputNode(TLImp)
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case class TLClientNode(params: TLClientParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SourceNode(TLImp)(TLClientPortParameters(Seq(params)), numPorts)
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case class TLManagerNode(beatBytes: Int, params: TLManagerParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SinkNode(TLImp)(TLManagerPortParameters(Seq(params), beatBytes), numPorts)
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case class TLAdapterNode(
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clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
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managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
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numClientPorts: Range.Inclusive = 1 to 1,
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numManagerPorts: Range.Inclusive = 1 to 1)
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extends InteriorNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts)
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