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tilelink2: relax max transfer size; the real requirement is not exceeding alignment

This commit is contained in:
Wesley W. Terpstra 2016-09-05 19:45:16 -07:00
parent cf0291061d
commit ded246fb95
2 changed files with 5 additions and 3 deletions
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1
src/main/scala/uncore/tilelink2/Fragmenter.scala
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@ -17,7 +17,6 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
require (isPow2 (maxSize))
require (isPow2 (minSize))
require (minSize < maxSize)
require (maxSize <= TransferSizes.maxAllowed)
val fragmentBits = log2Ceil(maxSize / minSize)

7
src/main/scala/uncore/tilelink2/Parameters.scala
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@ -50,7 +50,6 @@ case class TransferSizes(min: Int, max: Int)
require (min >= 0 && max >= 0)
require (max == 0 || isPow2(max))
require (min == 0 || isPow2(min))
require (max <= TransferSizes.maxAllowed)
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
@ -70,7 +69,6 @@ case class TransferSizes(min: Int, max: Int)
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
val maxAllowed = 4096 // transfers larger than 4kB are forbidden in TL2
implicit def asBool(x: TransferSizes) = !x.none
}
@ -130,6 +128,11 @@ case class TLManagerParameters(
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
// The device had better not support a transfer larger than it's alignment
address.foreach({ case a =>
require (a.alignment1 >= maxTransfer-1)
})
}
case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes: Int)