tilelink2: connect Nodes to LazyModules for better error messages
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		@@ -3,12 +3,13 @@
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package uncore.tilelink2
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import Chisel._
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import chisel3.internal.sourceinfo._
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import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo}
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abstract class LazyModule
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{
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  protected[tilelink2] var bindings = List[() => Unit]()
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  protected[tilelink2] var children = List[LazyModule]()
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  protected[tilelink2] var nodes = List[RootNode]()
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  protected[tilelink2] var info: SourceInfo = UnlocatableSourceInfo
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  protected[tilelink2] val parent = LazyModule.stack.headOption
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@@ -22,6 +23,12 @@ abstract class LazyModule
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    }
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  }
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  def name = getClass.getName.split('.').last
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  def line = info match {
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    case SourceLine(filename, line, col) => s" ($filename:$line:$col)"
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    case _ => ""
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  }
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  def module: LazyModuleImp
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  implicit val lazyModule = this
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@@ -55,6 +62,6 @@ abstract class LazyModuleImp(outer: LazyModule) extends Module
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  // .module had better not be accessed while LazyModules are still being built!
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  require (LazyModule.stack.isEmpty)
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  override def desiredName = outer.getClass.getName.split('.').last
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  override def desiredName = outer.name
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  outer.instantiate()
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}
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@@ -19,11 +19,20 @@ abstract class NodeImp[PO, PI, EO, EI, B <: Data]
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  def connect(bo: B, eo: EO, bi: B, ei: EI)(implicit sourceInfo: SourceInfo): Unit
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}
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class RootNode
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{
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  // You cannot create a Node outside a LazyModule!
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  require (!LazyModule.stack.isEmpty)
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  val lazyModule = LazyModule.stack.head
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  lazyModule.nodes = this :: lazyModule.nodes
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}
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class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(
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  private val oFn: Option[Seq[PO] => PO],
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  private val iFn: Option[Seq[PI] => PI],
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  private val numPO: Range.Inclusive,
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  private val numPI: Range.Inclusive)
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  private val numPI: Range.Inclusive) extends RootNode
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{
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  // At least 0 ports must be supported
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  require (!numPO.isEmpty)
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@@ -42,8 +51,12 @@ class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(
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  private var oRealized  = false
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  private var iRealized = false
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  private lazy val oPorts = { oRealized = true; require (numPO.contains(accPO.size)); accPO.result() }
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  private lazy val iPorts = { iRealized = true; require (numPI.contains(accPI.size)); accPI.result() }
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  def name = lazyModule.name + "." + getClass.getName.split('.').last
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  private def reqO() = require(numPO.contains(accPO.size), s"${name} has ${accPO.size} outputs, expected ${numPO}${lazyModule.line}")
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  private def reqI() = require(numPI.contains(accPI.size), s"${name} has ${accPI.size} inputs, expected ${numPI}${lazyModule.line}")
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  private lazy val oPorts = { oRealized = true; reqO(); accPO.result() }
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  private lazy val iPorts = { iRealized = true; reqI(); accPI.result() }
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  private lazy val oParams : Option[PO] = oFn.map(_(iPorts.map(_.oParams.get)))
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  private lazy val iParams : Option[PI] = iFn.map(_(oPorts.map(_.iParams.get)))
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