8e80d1ec80
Avoid floating-point arithmetic where integers suffice
2016-06-01 21:59:02 -07:00
13386af1d1
Get rid of unused implicit conversion
2016-06-01 19:30:41 -07:00
9949347569
First stab at debug interrupts
2016-06-01 16:57:10 -07:00
11b3cee07a
Ahb tweaks ( #50 )
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* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully
I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.
* ahb: optionally disable atomics => optimize to nothing
Trust the compiler the compiler to optimize away unused logic.
2016-06-01 16:42:39 -07:00
740a6073f6
Add Debug Module ( #49 )
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* Add Debug Module
* [debug] Remove unit tests, update System Bus register addresses, parameterize nComponents
* [debug] Update Debug ROM contents to match updated addresses
2016-06-01 16:33:33 -07:00
e8408f0a8a
fix HastiRAM
2016-06-01 10:33:59 -07:00
1311e78d3f
Add blocking D$ flush support
2016-05-31 19:28:41 -07:00
51379621d6
Flush blocking D$ on FENCE.I
2016-05-31 19:27:28 -07:00
6d82c0d156
Add M_FLUSH_ALL command
2016-05-31 19:25:31 -07:00
50e3caef36
get rid of Zscale file I missed last time
2016-05-31 14:33:38 -07:00
44a216038f
Use more generic TileLinkWidthAdapter
2016-05-27 13:38:13 -07:00
3ee5144923
Fix TLB tag check logic when ASIDs are present
2016-05-27 12:24:17 -07:00
8afdd7e3da
Work around PutBlocks draining into data array prematurely
2016-05-26 23:08:05 -07:00
c104b57c52
Use BitPat implicit conversion in instruction decoder
2016-05-26 22:23:21 -07:00
96fa1eb6ad
Add UInt->BitPat implicit conversion
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This will be removed from Chisel3, so we're putting it here to maintain
compatibility.
2016-05-26 18:52:53 -07:00
10f0e13c25
Use more parsimonious queue depths
2016-05-26 18:04:22 -07:00
3cc236e9c4
By default, use same TileLink width everywhere
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When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
2016-05-26 18:04:01 -07:00
391a9b9110
Use buses, rather than crossbars, by default in TLInterconnect
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We should eventually parameterize this, of course.
2016-05-26 16:10:42 -07:00
b6d26e90f8
Add generic TileLink width adapter
2016-05-26 15:59:42 -07:00
8139f71dfb
Work around Chisel2 bug
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This code is correct, but Chisel2 erroneously flags it as a Chisel3
compatibility error because it looks like Vec(Reg) when factor=1.
2016-05-26 12:37:31 -07:00
0c50bfcfb3
Work around more zero-width wire cases
2016-05-25 21:47:48 -07:00
22568de5f3
Work around another zero-width wire limitation
2016-05-25 21:42:02 -07:00
e2755a0f0a
Work around zero-width wire limitation in HTIF
2016-05-25 20:39:53 -07:00
3e238adc67
rtc: fix acquire message type check
2016-05-25 20:37:48 -07:00
40f38dde63
Work around lack of zero-width wires in D$
2016-05-25 19:44:31 -07:00
976d4d3184
ahb: AHB parameters should match TileLink parameters by default
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Closes #116
2016-05-25 18:01:25 -07:00
ec0d178010
Support M-mode-only implementations
2016-05-25 15:40:53 -07:00
00ea9a7d82
Remove most of mstatus when user mode isn't supported
2016-05-25 15:37:32 -07:00
5442b89664
Remove unnecessary muxes in RV32 MulDiv
2016-05-25 14:27:02 -07:00
9aa724706e
Don't include RV64 instructions in RV32 decode table
2016-05-25 14:26:45 -07:00
7f1792cba3
ahb: backport bridge to chisel2
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Closes #47
2016-05-25 13:40:24 -07:00
da105a5944
Don't allow travis to recurse through submodules
2016-05-25 13:27:49 -07:00
da566e7d6a
build: use local sbt when building firrtl
2016-05-25 11:48:03 -07:00
e82c080c3c
Add blocking D$
2016-05-25 11:09:50 -07:00
a8462d3cfc
bump chisel
2016-05-25 11:09:50 -07:00
c49cb10c74
Merge pull request #42 from terpstra/ahb
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Ahb
2016-05-24 17:02:15 -07:00
4605b616c1
Fix bug in D$ AMO/storegen logic
2016-05-24 16:26:07 -07:00
88cc91db75
Ignore way_en in MetadataArray for direct-mapped caches
2016-05-24 15:47:09 -07:00
5dac7b818d
Support set associativity in blocking D$
2016-05-24 15:45:52 -07:00
e0addb5723
Support uncached AMOs in blocking D$
2016-05-24 15:45:35 -07:00
f14d87e327
Support larger I$ sets when VM is disabled
2016-05-24 15:44:59 -07:00
3b35c7470e
Add uncached support to blocking D$
2016-05-24 15:05:41 -07:00
42f079ce57
JAL requires DW_XPR
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This has been benign so far because of how the logic minimization worked.
2016-05-24 15:05:41 -07:00
b92c73e361
Add LR/SC to blocking D$
2016-05-24 15:05:41 -07:00
0d93d1a1a0
Clean up pending store logic a bit
2016-05-24 15:05:41 -07:00
0b8de578d4
Add additional D$ store buffering to prevent structural hazards
2016-05-24 15:05:41 -07:00
354cb2d5ec
Don't stall I$ response when resolving a branch misprediction
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This avoids a fetch bubble.
Not clear if this is the best way to do it. Perhaps this change should
instead be made to Frontend (i.e., ignore resp.ready when req.valid is
high), but that might exacerbate a critical path.
2016-05-24 15:05:41 -07:00
d7790ac6a4
WIP on blocking D$
2016-05-24 15:05:41 -07:00
335e2c8a1e
Support disabling atomics extension
2016-05-24 15:05:41 -07:00
765b90f6a4
Stall on D$ lockups less conservatively
2016-05-24 15:05:41 -07:00
