riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman
8e80d1ec80 Avoid floating-point arithmetic where integers suffice 2016-06-01 21:59:02 -07:00
Andrew Waterman
13386af1d1 Get rid of unused implicit conversion 2016-06-01 19:30:41 -07:00
Andrew Waterman
9949347569 First stab at debug interrupts 2016-06-01 16:57:10 -07:00
Wesley W. Terpstra
11b3cee07a Ahb tweaks (#50) 
* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully

I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.

* ahb: optionally disable atomics => optimize to nothing

Trust the compiler the compiler to optimize away unused logic.
 2016-06-01 16:42:39 -07:00
mwachs5
740a6073f6 Add Debug Module (#49) 
* Add Debug Module

* [debug] Remove unit tests, update System Bus register addresses, parameterize nComponents

* [debug] Update Debug ROM contents to match updated addresses
 2016-06-01 16:33:33 -07:00
Howard Mao
e8408f0a8a fix HastiRAM 2016-06-01 10:33:59 -07:00
Andrew Waterman
1311e78d3f Add blocking D$ flush support 2016-05-31 19:28:41 -07:00
Andrew Waterman
51379621d6 Flush blocking D$ on FENCE.I 2016-05-31 19:27:28 -07:00
Andrew Waterman
6d82c0d156 Add M_FLUSH_ALL command 2016-05-31 19:25:31 -07:00
Howard Mao
50e3caef36 get rid of Zscale file I missed last time 2016-05-31 14:33:38 -07:00
Andrew Waterman
44a216038f Use more generic TileLinkWidthAdapter 2016-05-27 13:38:13 -07:00
Andrew Waterman
3ee5144923 Fix TLB tag check logic when ASIDs are present 2016-05-27 12:24:17 -07:00
Andrew Waterman
8afdd7e3da Work around PutBlocks draining into data array prematurely 2016-05-26 23:08:05 -07:00
Andrew Waterman
c104b57c52 Use BitPat implicit conversion in instruction decoder 2016-05-26 22:23:21 -07:00
Andrew Waterman
96fa1eb6ad Add UInt->BitPat implicit conversion 
This will be removed from Chisel3, so we're putting it here to maintain
compatibility.
 2016-05-26 18:52:53 -07:00
Andrew Waterman
10f0e13c25 Use more parsimonious queue depths 2016-05-26 18:04:22 -07:00
Andrew Waterman
3cc236e9c4 By default, use same TileLink width everywhere 
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
 2016-05-26 18:04:01 -07:00
Andrew Waterman
391a9b9110 Use buses, rather than crossbars, by default in TLInterconnect 
We should eventually parameterize this, of course.
 2016-05-26 16:10:42 -07:00
Andrew Waterman
b6d26e90f8 Add generic TileLink width adapter 2016-05-26 15:59:42 -07:00
Andrew Waterman
8139f71dfb Work around Chisel2 bug 
This code is correct, but Chisel2 erroneously flags it as a Chisel3
compatibility error because it looks like Vec(Reg) when factor=1.
 2016-05-26 12:37:31 -07:00
Andrew Waterman
0c50bfcfb3 Work around more zero-width wire cases 2016-05-25 21:47:48 -07:00
Andrew Waterman
22568de5f3 Work around another zero-width wire limitation 2016-05-25 21:42:02 -07:00
Andrew Waterman
e2755a0f0a Work around zero-width wire limitation in HTIF 2016-05-25 20:39:53 -07:00
Andrew Waterman
3e238adc67 rtc: fix acquire message type check 2016-05-25 20:37:48 -07:00
Andrew Waterman
40f38dde63 Work around lack of zero-width wires in D$ 2016-05-25 19:44:31 -07:00
Wesley W. Terpstra
976d4d3184 ahb: AHB parameters should match TileLink parameters by default 
Closes #116
 2016-05-25 18:01:25 -07:00
Andrew Waterman
ec0d178010 Support M-mode-only implementations 2016-05-25 15:40:53 -07:00
Andrew Waterman
00ea9a7d82 Remove most of mstatus when user mode isn't supported 2016-05-25 15:37:32 -07:00
Andrew Waterman
5442b89664 Remove unnecessary muxes in RV32 MulDiv 2016-05-25 14:27:02 -07:00
Andrew Waterman
9aa724706e Don't include RV64 instructions in RV32 decode table 2016-05-25 14:26:45 -07:00
Wesley W. Terpstra
7f1792cba3 ahb: backport bridge to chisel2 
Closes #47
 2016-05-25 13:40:24 -07:00
Andrew Waterman
da105a5944 Don't allow travis to recurse through submodules 2016-05-25 13:27:49 -07:00
Wesley W. Terpstra
da566e7d6a build: use local sbt when building firrtl 2016-05-25 11:48:03 -07:00
Andrew Waterman
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Andrew Waterman
a8462d3cfc bump chisel 2016-05-25 11:09:50 -07:00
Andrew Waterman
c49cb10c74 Merge pull request #42 from terpstra/ahb 
Ahb
 2016-05-24 17:02:15 -07:00
Andrew Waterman
4605b616c1 Fix bug in D$ AMO/storegen logic 2016-05-24 16:26:07 -07:00
Andrew Waterman
88cc91db75 Ignore way_en in MetadataArray for direct-mapped caches 2016-05-24 15:47:09 -07:00
Andrew Waterman
5dac7b818d Support set associativity in blocking D$ 2016-05-24 15:45:52 -07:00
Andrew Waterman
e0addb5723 Support uncached AMOs in blocking D$ 2016-05-24 15:45:35 -07:00
Andrew Waterman
f14d87e327 Support larger I$ sets when VM is disabled 2016-05-24 15:44:59 -07:00
Andrew Waterman
3b35c7470e Add uncached support to blocking D$ 2016-05-24 15:05:41 -07:00
Andrew Waterman
42f079ce57 JAL requires DW_XPR 
This has been benign so far because of how the logic minimization worked.
 2016-05-24 15:05:41 -07:00
Andrew Waterman
b92c73e361 Add LR/SC to blocking D$ 2016-05-24 15:05:41 -07:00
Andrew Waterman
0d93d1a1a0 Clean up pending store logic a bit 2016-05-24 15:05:41 -07:00
Andrew Waterman
0b8de578d4 Add additional D$ store buffering to prevent structural hazards 2016-05-24 15:05:41 -07:00
Andrew Waterman
354cb2d5ec Don't stall I$ response when resolving a branch misprediction 
This avoids a fetch bubble.

Not clear if this is the best way to do it.  Perhaps this change should
instead be made to Frontend (i.e., ignore resp.ready when req.valid is
high), but that might exacerbate a critical path.
 2016-05-24 15:05:41 -07:00
Andrew Waterman
d7790ac6a4 WIP on blocking D$ 2016-05-24 15:05:41 -07:00
Andrew Waterman
335e2c8a1e Support disabling atomics extension 2016-05-24 15:05:41 -07:00
Andrew Waterman
765b90f6a4 Stall on D$ lockups less conservatively 2016-05-24 15:05:41 -07:00