riscv/rocket-chip
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  • c9e1b72972 Don't assign SInt(-1) to a UInt Palmer Dabbelt 2016-03-14 16:53:55 -0700
  • 3b0e87f42a pass CSRs through to ground test and get DMA tests working again Howard Mao 2016-03-22 20:00:28 -0700
  • 7b7e954133 make sure DummyPTW does not invalidate the TLB Howard Mao 2016-03-22 19:59:58 -0700
  • 6da45e7f26 Trace generator: updates and additions to the scripts directory. Matthew Naylor 2016-03-18 12:24:12 +0000
  • aa22f175c3 Add cloneType methods for Chisel3 Palmer Dabbelt 2016-03-14 14:12:21 -0700
  • c989ec5813 Fix the SCR file for Chisel 3 Palmer Dabbelt 2016-03-05 17:20:25 -0800
  • 1344d09cef Fix the SCR file for Chisel 3 Palmer Dabbelt 2016-03-05 17:20:54 -0800
  • bda5772e98 Updates to the trace-generator: (1) Don't terminate via HTIF exit, which can cause other, unfinished, cores to be cut short. Instead emit FINISHED messsages allowing an external process to send a SIGTERM to the emulator once all cores have finished. (2) Add some support for greater address variation without having to recompile, disabled by default. (3) Generate atomic, LR/SC, and fence operations by default in addition to plain loads and stores. These changes require newer versions of files in the rocket-chip/scripts directory. I will submit a pull request for those too. Matthew Naylor 2016-03-18 12:11:11 +0000
  • c13b8d243d BroadcastHub race on allocating VolWBs vs Acquires Henry Cook 2016-03-17 18:32:35 -0700
  • 5f3d3a0b2d Bugfix for probe flags in L2BroadcastHub Henry Cook 2016-03-17 16:42:40 -0700
  • 49d82864bf Fix StoreDataQueue allocation bug in BroadcastHub Henry Cook 2016-03-17 12:31:18 -0700
  • b5992186df include top-level makefrag in regressions Colin Schmidt 2016-03-16 15:09:42 -0700
  • e90a9dfb2b make taking max of multiple integers in config a bit easier Howard Mao 2016-03-16 14:21:47 -0700
  • 4fc2a14a63 Fix MIF bug that cuts off upper xact id bits Eric Love 2016-03-11 16:59:24 -0800
  • 8a47c3f346 Make sure there's enough xact id bits Eric Love 2016-03-11 16:54:56 -0800
  • 04be438847 Avoid conflicting assigments to registers in timers. Give priority to start over stop. Matthew Naylor 2016-03-10 12:50:03 +0000
  • 137b77d780 Merge pull request #4 from ucb-bar/chisel3 Andrew Waterman 2016-03-15 17:30:34 -0700
  • 50f61687de Work around Chisel3's lack of 0-width wires Palmer Dabbelt 2016-03-14 13:12:43 -0700
  • 9dc0cbdfa4 WIP on privileged spec v1.9 Andrew Waterman 2016-03-14 18:03:33 -0700
  • 13dcb96b7f Update TLB interface Andrew Waterman 2016-03-14 17:55:19 -0700
  • 648437e7cb Merge pull request #70 from ucb-bar/add-rv32-support Andrew Waterman 2016-03-14 17:06:39 -0700
  • db09f310a1 Define MIFMasterTagBits as # bits a master can *use* in tag Eric Love 2016-03-11 16:48:13 -0800
  • f2ded2721d Merge branch 'master' into add-rv32-support Andrew Waterman 2016-03-10 19:33:04 -0800
  • 25091003af Add RV32 test/configuration options Andrew Waterman 2016-03-10 17:40:21 -0800
  • 67e711844a index extraction bug Henry Cook 2016-03-10 17:35:22 -0800
  • e2185d40f6 Avoid right-shift by larger that the bit width Palmer Dabbelt 2016-03-06 16:32:59 -0800
  • 8c7e29eacd Avoid generating 0-width UInts Palmer Dabbelt 2016-03-06 16:32:14 -0800
  • 2eafc4c8f3 Extend AMOALU to support RV32 Andrew Waterman 2016-03-10 17:19:42 -0800
  • c28d115b30 Chisel3 compatibility fix Andrew Waterman 2016-03-10 15:50:44 -0800
  • 7ae44d4905 Add RV32 support Andrew Waterman 2016-03-10 17:32:00 -0800
  • 82c595d11a Fix no-FPU elaboration of CSR file Andrew Waterman 2016-03-10 17:30:56 -0800
  • 93773a4496 Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks. Henry Cook 2016-03-06 23:12:16 -0800
  • 67ad36d74a Merge pull request #69 from ucb-bar/fix-tabs Andrew Waterman 2016-03-10 16:17:46 -0800
  • 7a75a03123 tabs are evil Andrew Waterman 2016-03-10 14:17:41 -0800
  • 3c9e63f5a5 don't make HTIF clock divider tied to backup memory Howard Mao 2016-03-09 13:56:50 -0800
  • 3e721fe80b Merge pull request #2 from ucb-bar/chisel3 Andrew Waterman 2016-03-06 04:27:52 -0800
  • bf06ba0d37 Pass a BitPat to Lookup Palmer Dabbelt 2016-03-05 18:50:56 -0800
  • 36f2e6504c Fix width of NastiROM rows, preventing out-of-range extraction Andrew Waterman 2016-03-03 16:56:53 -0800
  • bc15e8649e WIP on priv spec v1.9 Andrew Waterman 2016-03-02 23:29:58 -0800
  • 5e145515e1 fix some Chisel assertions Howard Mao 2016-03-02 14:03:15 -0800
  • 7eef3393f1 fix bug resulting in different g_types on tail beats in L2CacheBank.io.inner.grant Henry Cook 2016-03-02 10:59:18 -0800
  • 57370bdf49 first and last on HasTileLinkData Henry Cook 2016-03-01 15:45:35 -0800
  • 9c7e5bc6c0 bump hardfloat, tools(tests & spike) for fcvt fix Colin Schmidt 2016-03-01 19:53:08 -0800
  • a80b0e959d Add support for per-way cache metadata Albert Magyar 2016-02-29 14:49:18 -0800
  • 4acdc67485 Add an assertion in the NastiIOTileLink converter Palmer Dabbelt 2016-02-26 18:36:47 -0800
  • ab30983aa9 Add support for per-way cache metadata Albert Magyar 2016-02-29 14:48:49 -0800
  • a9380a3dc1 bump hardfloat,uncore,chisel,tools(tests) for sqrt fix Colin Schmidt 2016-02-29 16:09:52 -0800
  • 6d984273b7 finally fix all release assertions ... hopefully Howard Mao 2016-02-29 15:22:24 -0800
  • 760893e448 add makefile for float_fix and comlog tools Howard Mao 2016-02-29 11:24:53 -0800
  • be8a411f9c get rid of axe submodule and move toaxe.py script to scripts Howard Mao 2016-02-29 10:57:58 -0800
  • ba96ad2b38 Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip John Wright 2016-02-25 10:40:47 -0800
  • 6095e7361e Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip John Wright 2016-02-25 10:39:43 -0800
  • 7fa38b5624 Merge pull request #68 from ucb-bar/test-and-fix-backup-mem Palmer Dabbelt 2016-02-27 12:19:55 -0800
  • a0f3189c74 Change MIF_DATA_BITS back to 64 Palmer Dabbelt 2016-02-27 11:41:28 -0800
  • 9ea8c4e781 Add an 8-channel backup memory port config Palmer Dabbelt 2016-02-26 01:33:25 -0800
  • 7319f430d0 Fix the backup memory port on multiple-channel configs Palmer Dabbelt 2016-02-27 10:35:22 -0800
  • 7c0c48fac4 Resurrect the backup memory port Palmer Dabbelt 2016-02-26 01:29:38 -0800
  • 68a49c7700 fetch rocketchip_addons during regression submodule step Colin Schmidt 2016-02-26 11:05:41 -0800
  • 8c73d10fe1 Support SCR address generation with __OFFSET at the end Palmer Dabbelt 2016-02-25 21:57:37 -0800
  • ebffd69b8e Provide both __OFFSET and __PADDR for SCR entries Palmer Dabbelt 2016-02-25 21:48:32 -0800
  • 640204b221 Merge pull request #66 from ucb-bar/rocc-ptw-refactoring Andrew Waterman 2016-02-25 18:01:01 -0800
  • 091782ad27 Merge pull request #29 from ucb-bar/rocc-ptw-refactoring Andrew Waterman 2016-02-25 17:57:22 -0800
  • a2381d2faf RoCC PTW refactoring Yunsup Lee 2016-02-24 22:52:02 -0800
  • 15ac4d317f RoCC PTW refactoring Yunsup Lee 2016-02-24 22:39:00 -0800
  • ef4915bd2c make the asm suites ordered by their insertion order Colin Schmidt 2016-02-24 15:23:37 -0800
  • ad81d95751 add run-asm-{p,pt,v}-tests targets for convenience Colin Schmidt 2016-02-24 15:04:13 -0800
  • b04cd545b6 pass base SCR address to SCRFile for address calculation John Wright 2016-02-22 20:17:33 -0800
  • 19420cd5df add utility overloads of SCRIO.attach, pass base address so that generated c header is correct, and print debug messages/header in hex instead of decimal John Wright 2016-02-22 20:15:57 -0800
  • 8a877fa620 Add Matthew Naylor's trace generator and AXE scripts Howard Mao 2016-02-22 10:04:38 -0800
  • 8c02cb09ca some additions to Travis and fixes for Testing Howard Mao 2016-02-23 16:56:13 -0800
  • 90a73c621d Merge pull request #58 from ucb-bar/more-travis-fixing Palmer Dabbelt 2016-02-23 21:26:16 -0800
  • 58d6af207f Cache all the Scala build directories Palmer Dabbelt 2016-02-23 16:47:48 -0800
  • 4f5b1da58b add a resp_len helper to AtosRequest Howard Mao 2016-02-16 10:02:48 -0800
  • db3b2c264c Add constructors, converters, and serdes for AXI tunneled over SERDES (AtoS) Howard Mao 2016-01-21 17:39:57 -0800
  • c263c636b3 Actually reference all the tests from RISCV Palmer Dabbelt 2016-02-23 16:05:27 -0800
  • 8873222e42 fix cache release assertion Howard Mao 2016-02-23 16:03:51 -0800
  • ad62afd9ca Add zscale to regression submodule list Palmer Dabbelt 2016-02-23 12:58:08 -0800
  • 700d756de0 Merge pull request #55 from ucb-bar/travis-regression Palmer Dabbelt 2016-02-23 12:19:59 -0800
  • bae4c0c0c9 Point Testing to $RISCV/... not $base_dir/... Palmer Dabbelt 2016-02-23 10:57:46 -0800
  • 1e49eb4958 format .travis.yml (trigger rebuilt to test cache) Colin Schmidt 2016-02-23 08:44:15 -0800
  • e097cdcef8 bump tools for install tests fix Colin Schmidt 2016-02-23 07:42:54 -0800
  • 28c91795c3 Enable travis caching Palmer Dabbelt 2016-02-22 17:41:01 -0800
  • edd0b3b824 Move travis to the regression Makefile Palmer Dabbelt 2016-02-22 17:29:07 -0800
  • c2e9971b5f move toaxe.py script into top-level Rocket-Chip repo Howard Mao 2016-02-23 08:52:32 -0800
  • 1b6871f3d8 Add author, affiliation, and sponsor info to trace-generator files. Matthew Naylor 2016-02-23 15:30:11 +0000
  • 0ac5c07683 Merge pull request #54 from ucb-bar/fsim-no-htif Palmer Dabbelt 2016-02-22 20:02:03 -0800
  • a073c37e36 The FPGA doesn't have an HTIF clock divider Palmer Dabbelt 2016-02-22 15:30:19 -0800
  • c1b5f71ee7 don't run bmarks in parallel Colin Schmidt 2016-02-22 13:34:24 -0800
  • 4ce603e548 Memtest configs should not have a hex file loaded Colin Schmidt 2016-02-22 12:49:26 -0800
  • 91e3c9b96f reuse generator parameters for tracegen Howard Mao 2016-02-22 09:53:31 -0800
  • 43c2237ef7 add more memtest configs and remove channel test Colin Schmidt 2016-02-22 09:38:44 -0800
  • 0c575403af only use a single asm test and 1 bmark for memtest Colin Schmidt 2016-02-22 09:07:26 -0800
  • e4c4a90648 add a config to travis for memchannel mux select Colin Schmidt 2016-02-19 16:12:52 -0800
  • 3dae576c9e add travis configs for memtest Colin Schmidt 2016-02-19 16:05:15 -0800
  • e63fc3bb44 Added trace generator Matthew Naylor 2016-02-18 20:41:04 +0000
  • 4fedd180ee bump uncore and groundtest Howard Mao 2016-02-19 23:31:09 -0800
  • da302504a5 get rid of sequential same id get regression in broadcast regression suite Howard Mao 2016-02-19 23:14:34 -0800
  • 85cc632d5d fix emulator debug build Howard Mao 2016-02-19 23:13:57 -0800
  • 929d8e31f7 refactor ready/valid logic for routing release messages in the l2 Henry Cook 2016-02-10 11:12:43 -0800
  • 5e4a02038c move FPGA AXI to HTIF converter into Chisel module Howard Mao 2016-02-19 13:30:20 -0800