riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

add utility overloads of SCRIO.attach, pass base address so that generated c header is correct, and print debug messages/header in hex instead of decimal

Browse Source
This commit is contained in:
John Wright 2016-02-22 20:15:57 -08:00 committed by Howard Mao
parent 8873222e42
commit 19420cd5df
1 changed files with 44 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
uncore/src/main/scala/scr.scala
View File

@ -8,7 +8,7 @@ import scala.collection.mutable.ArrayBuffer
/** Stores a map between SCR file names and address in the SCR file, which can
* later be dumped to a header file for the test bench. */
class SCRFileMap(prefix: String, maxAddress: Int) {
class SCRFileMap(prefix: String, maxAddress: Int, baseAddress: BigInt) {
private val addr2name = HashMap.empty[Int, String]
private val name2addr = HashMap.empty[String, Int]
@ -18,7 +18,7 @@ class SCRFileMap(prefix: String, maxAddress: Int) {
Predef.assert(address < maxAddress, "address too large")
addr2name += (address -> name)
name2addr += (name -> address)
println(prefix + ": " + address + " -> " + name)
println(prefix + ": %x -> ".format(baseAddress + address) + name)
address
}
@ -29,7 +29,7 @@ class SCRFileMap(prefix: String, maxAddress: Int) {
def as_c_header(): String = {
addr2name.map{ case(address, name) =>
"#define " + prefix + "__" + name + " " + address
"#define " + prefix + "__" + name + " 0x%x".format(baseAddress + address)
}.mkString("\n") + "\n"
}
}
@ -40,22 +40,57 @@ class SCRIO(map: SCRFileMap)(implicit p: Parameters) extends HtifBundle()(p) {
val waddr = UInt(OUTPUT, log2Up(nSCR))
val wdata = Bits(OUTPUT, scrDataBits)
def attach(reg: Data, name: String): Data = {
def attach(regs: Seq[Data]): Seq[Data] = {
regs.zipWithIndex.map{ case(reg, i) => attach(reg) }
}
def attach(regs: Seq[Data], name_base: String): Seq[Data] = {
regs.zipWithIndex.map{ case(reg, i) => attach(reg, name_base + "__" + i) }
}
def attach(data: Data): Data = attach(data, data.name, false, false)
def attach(data: Data, name: String): Data = attach(data, name, false, false)
def attach(data: Data, addReg: Boolean): Data = attach(data, data.name, false, false)
def attach(data: Data, addReg: Boolean, readOnly: Boolean): Data = attach(data, data.name, readOnly, false)
def attach(data: Data, name: String, addReg: Boolean): Data = attach(data, name, addReg, false)
def attach(data: Data, name: String, addReg: Boolean, readOnly: Boolean): Data = {
val addr = map.allocate(name)
when (wen && (waddr === UInt(addr))) {
reg := wdata
val reg = if(addReg) { Reg(init = Bits(0, width=data.getWidth)) } else { data }
if (!readOnly) {
when (wen && (waddr === UInt(addr))) {
reg := wdata(data.getWidth-1,0)
}
}
require(data.getWidth <= scrDataBits, "SCR Width must be <= %d for %s".format(scrDataBits,name))
if (data.getWidth < scrDataBits) {
rdata(addr) := Cat(UInt(0, width=(scrDataBits-data.getWidth)),reg)
} else {
rdata(addr) := reg
}
rdata(addr) := reg
reg
}
def attach(bundle: Bundle): Array[Data] = attach(bundle, "")
def attach(bundle: Bundle, prefix: String): Array[Data] = {
bundle.flatten.map { x =>
if (x._2.dir == OUTPUT) {
attach(x._2, prefix + x._1, false, true)
} else {
attach(x._2, prefix + x._1, true)
}
}
}
def allocate(address: Int, name: String): Unit = {
map.allocate(address, name)
}
}
class SCRFile(prefix: String)(implicit p: Parameters) extends HtifModule()(p) {
val map = new SCRFileMap(prefix, 64)
class SCRFile(prefix: String, baseAddress: BigInt)(implicit p: Parameters) extends HtifModule()(p) {
val map = new SCRFileMap(prefix, 64, baseAddress)
AllSCRFiles += map
val io = new Bundle {