Avoid right-shift by larger that the bit width
FIRRTL bails out on this. There's an outstanding bug, this is just a workaround. See https://github.com/ucb-bar/firrtl/issues/69
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@ -1110,8 +1110,15 @@ abstract class TileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) exte
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trait AppendsArbiterId extends TileLinkArbiterLike {
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def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) =
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Cat(in.client_xact_id, UInt(id, log2Up(arbN)))
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def managerSourcedClientXactId(in: ManagerSourcedWithId) =
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in.client_xact_id >> log2Up(arbN)
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def managerSourcedClientXactId(in: ManagerSourcedWithId) = {
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/* This shouldn't be necessary, but Chisel3 doesn't emit correct Verilog
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* when right shifting by too many bits. See
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* https://github.com/ucb-bar/firrtl/issues/69 */
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if (in.client_xact_id.getWidth > log2Up(arbN))
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in.client_xact_id >> log2Up(arbN)
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else
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UInt(0)
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}
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def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id(log2Up(arbN)-1,0).toUInt
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}
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