Added trace generator
This commit is contained in:
Matthew Naylor
Howard Mao
parent
da302504a5
commit
e63fc3bb44
148
groundtest/scripts/toaxe.py
Executable file
148
groundtest/scripts/toaxe.py
Executable file
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#!/usr/bin/env python
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# This script takes memory-subsystem traces produced by the groundtest
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# trace generator (see tracegen.scala) and puts them into a format
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# that can be validated by the axe tool (see
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# https://github.com/CTSRD-CHERI/axe).
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import sys
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import re
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if len(sys.argv) != 2:
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print "Usage: toaxe.py [FILE]"
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sys.exit()
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if sys.argv[1] == "-":
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f = sys.stdin
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else:
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f = open(sys.argv[1], 'r')
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if f == None:
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print "File not found: ", sys.argv[1]
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sys.exit()
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lineCount = 0
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def error(msg):
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print "Error at line ", lineCount, ": ", msg
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sys.exit()
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# Mapping from address to axe address
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addrMap = {}
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nextAddr = 0
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# Mapping from (thread id, tag id) to axe operation id
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tagMap = {}
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# Mapping from thread id to operation id
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fenceReq = {}
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# Mapping from thread id to operation id
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loadReserve = {}
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# Array of axe operations
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ops = []
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for line in f:
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# Exit loop at end of trace
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if line[0:9] == 'Completed': break
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# Parse thread id and command
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m = re.search(' *([0-9]+) *: *([^ ]*) (.*)', line)
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if m == None: error("Expected: <thread-id> ':' <command>")
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tid, cmd, line = m.group(1), m.group(2), m.group(3)
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if cmd == 'fence-req':
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# Parse time
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m = re.search(' *@ *([0-9]+)', line)
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if m == None: error ("expected timestamp")
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# Insert placeholder containing request time
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ops.append(str(m.group(1)))
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fenceReq[tid] = len(ops)-1
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elif cmd == 'fence-resp':
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# Insert 'sync' operation
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if not (tid in fenceReq) or fenceReq[tid] == None:
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error("fence-resp without fence-req on thread " + tid)
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startTime = ops[fenceReq[tid]]
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op = str(tid) + ": sync @ " + startTime
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# Add end-time
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m = re.search(' *@ *([0-9]+)', line)
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if m != None: op = op + ":" + str(m.group(1))
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ops[fenceReq[tid]] = (op,)
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fenceReq[tid] = None
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elif cmd == 'load-req' or cmd == 'load-reserve-req':
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# Parse address, tag, and time
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m = re.search(' *([0-9a-fx]+) *# *([0-9]+) *@ *([0-9]+)', line)
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if m == None: error("expected <address> #<tag> @<timestamp>")
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# Update address map
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if not (m.group(1) in addrMap):
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addrMap[m.group(1)] = nextAddr
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nextAddr = nextAddr+1
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# Insert place-holder
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ops.append((cmd, None, addrMap[m.group(1)], m.group(3), None))
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tagMap[(tid, m.group(2))] = len(ops)-1
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if cmd == 'load-reserve-req':
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loadReserve[tid] = len(ops)-1
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elif cmd == 'store-req' or cmd == 'store-cond-req' or cmd == 'swap-req':
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# Parse value, address, tag, and time
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m = re.search(' *([0-9]+) *([0-9a-fx]+) *# *([0-9]+) *@ *([0-9]+)', line)
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if m == None: error("expected <value> <address> #<tag> @<timestamp>")
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# Update address map
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if not (m.group(2) in addrMap):
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addrMap[m.group(2)] = nextAddr
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nextAddr = nextAddr+1
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# Insert place-holder
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lr = loadReserve[tid] if tid in loadReserve else None
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ops.append((cmd, m.group(1), addrMap[m.group(2)], m.group(4), lr))
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tagMap[(tid, m.group(3))] = len(ops)-1
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if cmd == 'store-cond-req': loadReserve[tid] = None
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elif cmd == 'resp':
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# Parse value and timestamp
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m = re.search(' *([0-9]+) *# *([0-9]+) *@ *([0-9]+)', line)
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if m == None: error("expected <value> #<tag> @<timestamp>")
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# Find corresponding response
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tag = m.group(2)
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if not ((tid, tag) in tagMap) or tagMap[(tid, tag)] == None:
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error("resp without associated req with tag " + tag + " on thread " + tid)
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opId = tagMap[(tid, tag)]
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(c, val, addr, start, lr) = ops[opId]
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if c == 'load-req':
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op = tid + ": M[" + str(addr) + '] == ' + m.group(1) + ' @ '
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op += start + ':' + m.group(3)
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ops[opId] = (op,)
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elif c == 'store-req':
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op = tid + ": M[" + str(addr) + '] := ' + val + ' @ '
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op += start + ':' # + m.group(3)
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ops[opId] = (op,)
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elif c == 'load-reserve-req':
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ops[opId] = (m.group(1), start, m.group(3))
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elif c == 'store-cond-req':
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if lr == None: error("store conditional without load-reserve")
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(loadVal, loadStart, loadFin) = ops[lr]
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if int(m.group(1)) != 0:
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# SC fail
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op = tid + ": M[" + str(addr) + "] == " + loadVal
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op += " @ " + loadStart + ":" + loadFin
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else:
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# SC success
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op = tid + ": { M[" + str(addr) + "] == " + loadVal + "; "
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op += "M[" + str(addr) + "] := " + val + "} @ "
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op += loadStart + ":" # + m.group(3)
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ops[lr] = (op,)
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ops[opId] = None
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elif c == 'swap-req':
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op = tid + ": { M[" + str(addr) + '] == ' + m.group(1)
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op += '; M[' + str(addr) + '] := ' + val
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op += '} @ ' + start + ':' # + m.group(3)
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ops[opId] = (op,)
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else:
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error("Unknown command '" + cmd + "'")
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lineCount = lineCount+1
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# Print address map in comments
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for addr in addrMap:
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print ("# &M[" + str(addrMap[addr]) + "] == " + addr)
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# Print axe trace
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for op in ops:
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if op != None and isinstance(op, tuple) and len(op) == 1:
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print op[0]
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499
groundtest/src/main/scala/tracegen.scala
Normal file
499
groundtest/src/main/scala/tracegen.scala
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@ -0,0 +1,499 @@
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// Generate memory traces that result from random sequences of memory
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// operations. These traces can then be validated by an external
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// tool. A trace is a simply sequence of memory requests and
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// responses.
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package groundtest
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import Chisel._
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import uncore._
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import junctions._
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import rocket._
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import scala.util.Random
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import cde.{Parameters, Field}
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// ==========================
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// Trace-generator parameters
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// ==========================
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// Compile-time parameters:
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//
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// * The id of the generator (there may be more than one in a
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// multi-core system).
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//
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// * The total number of generators present in the system.
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//
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// * The desired number of requests to be sent by each generator.
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//
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// * A list of physical addresses from which an address is drawn when
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// generating a fresh request.
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case object NumGens extends Field[Int]
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case object NumReqsPerGen extends Field[Int]
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case object AddressBag extends Field[List[Int]]
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trait HasTraceGenParams {
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implicit val p: Parameters
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val numGens = p(NumGens)
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val numBitsInId = log2Up(numGens)
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val numReqsPerGen = p(NumReqsPerGen)
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val memRespTimeout = 4096
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val numBitsInWord = p(WordBits)
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val numBytesInWord = numBitsInWord / 8
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val numBitsInWordOffset = log2Up(numBytesInWord)
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val addressBag = p(AddressBag)
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val logNumAddrsInTrace = log2Up(addressBag.length)
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require(numBytesInWord * 8 == numBitsInWord)
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require(1 << logNumAddrsInTrace == addressBag.length)
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}
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// ============
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// Trace format
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// ============
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// Let <id> denote a generator id;
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// <addr> denote an address (in hex);
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// <data> denote a value that is stored at an address;
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// <tag> denote a unique request/response id;
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// and <time> denote an integer representing a cycle-count.
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// Each line in the trace takes one of the following formats.
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//
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// <id>: load-req <addr> #<tag> @<time>
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// <id>: load-reserve-req <addr> #<tag> @<time>
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// <id>: store-req <data> <addr> #<tag> @<time>
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// <id>: store-cond-req <data> <addr> #<tag> @<time>
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// <id>: swap-req <data> <addr> #<tag> @<time>
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// <id>: resp <data> #<tag> @<time>
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// <id>: fence-req @<time>
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// <id>: fence-resp @<time>
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// NOTE: The (address, value) pair of every generated store is unique,
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// i.e. the same value is never written to the same address twice.
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// This aids trace validation.
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// ============
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// Random seeds
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// ============
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// The generator employs "unitialised registers" to seed its PRNGs;
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// these are randomly initialised by the C++ backend. This means that
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// the "-s" command-line argument to the Rocket emulator can be used
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// to generate new traces, or to replay specific ones.
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// ===========
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// Tag manager
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// ===========
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// This is used to obtain unique tags for memory requests: each
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// request must carry a unique tag since responses can come back
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// out-of-order.
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//
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// The tag manager can be viewed as a set of tags. The user can take
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// a tag out of the set (if there is one available) and later put it
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// back.
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class TagMan(val logNumTags : Int) extends Module {
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val io = new Bundle {
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// Is there a tag available?
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val available = Bool(OUTPUT)
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// If so, which one?
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val tagOut = UInt(OUTPUT, logNumTags)
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// User pulses this to take the currently available tag
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val take = Bool(INPUT)
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// User pulses this to put a tag back
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val put = Bool(INPUT)
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// And the tag put back is
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val tagIn = UInt(INPUT, logNumTags)
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}
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// Total number of tags available
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val numTags = 1 << logNumTags
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// For each tag, record whether or not it is in use
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val inUse = List.fill(numTags)(Reg(init = Bool(false)))
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// Mapping from each tag to its 'inUse' bit
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val inUseMap = (0 to numTags-1).map(i => UInt(i, logNumTags)).zip(inUse)
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// Next tag to offer
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val nextTag = Reg(init = UInt(0, logNumTags))
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io.tagOut := nextTag
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// Is the next tag available?
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io.available := ~Lookup(nextTag, Bool(true), inUseMap)
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// When user takes a tag
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when (io.take) {
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for ((i, b) <- inUseMap) {
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when (i === nextTag) { b := Bool(true) }
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}
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nextTag := nextTag + UInt(1)
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}
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// When user puts a tag back
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when (io.put) {
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for ((i, b) <- inUseMap) {
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when (i === io.tagIn) { b := Bool(false) }
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}
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}
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}
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// ===============
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// Trace generator
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// ===============
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class TraceGenerator(id: Int)
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(implicit p: Parameters) extends L1HellaCacheModule()(p)
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with HasTraceGenParams {
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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val mem = new HellaCacheIO
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}
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// Random addresses
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// ----------------
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// Address list taken from module parameters.
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val numAddrsInTrace = 1 << logNumAddrsInTrace
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val bagOfAddrs = addressBag.map(x => UInt(x, numBitsInWord))
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// A random index into the address bag.
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val randAddrIndex = Module(new LCG(logNumAddrsInTrace)).io.out
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// A random address from the address bag.
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val addrIndices = (0 to numAddrsInTrace-1).
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map(i => UInt(i, logNumAddrsInTrace))
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val randAddr = MuxLookup(randAddrIndex, UInt(0),
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addrIndices.zip(bagOfAddrs))
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// Random opcodes
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// --------------
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// Generate random opcodes for memory operations according to the
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// given frequency distribution.
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// Opcodes
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val (opNop :: opLoad :: opStore ::
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opFence :: opLRSC :: opSwap ::
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opDelay :: Nil) = Enum(Bits(), 7)
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// Distribution specified as a list of (frequency,value) pairs.
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// NOTE: frequencies must sum to a power of two.
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//val randOp = Frequency(List(
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// (10, opLoad),
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// (10, opStore),
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// (4, opFence),
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// (3, opLRSC),
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// (3, opSwap),
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// (2, opDelay)))
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// For now, just generate loads and stores as this is enough to
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// expose strange behaviour.
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val randOp = Frequency(List(
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(15, opLoad),
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(15, opStore),
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(2, opDelay)))
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// Request/response tags
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// ---------------------
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// Responses may come back out-of-order. Each request and response
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// therefore contains a unique 7-bit identifier, referred to as a
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// "tag", used to match each response with its corresponding request.
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// Create a tag manager giving out unique 3-bit tags
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val tagMan = Module(new TagMan(3))
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// Default inputs
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tagMan.io.take := Bool(false);
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tagMan.io.put := Bool(false);
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tagMan.io.tagIn := UInt(0);
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// Cycle counter
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// -------------
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// 32-bit cycle count used to record send-times of requests and
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// receive-times of respones.
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val cycleCount = Reg(init = UInt(0, 32))
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cycleCount := cycleCount + UInt(1);
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// Delay timer
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// -----------
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// Used to implement the delay operation and to insert random
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// delays between load-reserve and store-conditional commands.
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// A 16-bit timer is plenty
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val delayTimer = Module(new DynamicTimer(16))
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// Used to generate a random delay period
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val randDelayBase = Module(new LCG16()).io.out
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// Random delay period: usually small, occasionally big
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val randDelay = Frequency(List(
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(14, UInt(0, 13) ## randDelayBase(2, 0)),
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(2, UInt(0, 11) ## randDelayBase(5, 0))))
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// Default inputs
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delayTimer.io.start := Bool(false)
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delayTimer.io.period := randDelay
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delayTimer.io.stop := Bool(false)
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// Operation dispatch
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// ------------------
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// Hardware thread id
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val tid = UInt(id, numBitsInId)
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// Request & response count
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val reqCount = Reg(init = UInt(0, 32))
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val respCount = Reg(init = UInt(0, 32))
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// Current operation being executed
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val currentOp = Reg(init = opNop)
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// If larger than 0, a multi-cycle operation is in progress.
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// Value indicates stage of progress.
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val opInProgress = Reg(init = UInt(0, 2))
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// Indicate when a fresh request is to be sent
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val sendFreshReq = Wire(Bool())
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sendFreshReq := Bool(false)
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// Used to generate unique data values
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val nextData = Reg(init = UInt(1, numBitsInWord-numBitsInId))
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// Registers for all the interesting parts of a request
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val reqValid = Reg(init = Bool(false))
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val reqAddr = Reg(init = UInt(0, numBitsInWord))
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val reqData = Reg(init = UInt(0, numBitsInWord))
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val reqCmd = Reg(init = UInt(0, 5))
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val reqTag = Reg(init = UInt(0, 7))
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// Condition on being allowed to send a fresh request
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val canSendFreshReq = (!reqValid || io.mem.req.fire()) &&
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tagMan.io.available
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// Operation dispatch
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when (reqCount < UInt(numReqsPerGen)) {
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// No-op
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when (currentOp === opNop) {
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// Move on to a new operation
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currentOp := randOp
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}
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// Fence
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when (currentOp === opFence) {
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when (opInProgress === UInt(0) && !reqValid) {
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// Emit fence request
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printf("%d: fence-req @%d\n", tid, cycleCount)
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// Multi-cycle operation now in progress
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opInProgress := UInt(1)
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}
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// Wait until all requests have had a response
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.elsewhen (io.mem.ordered && reqCount === respCount) {
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// Emit fence response
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printf("%d: fence-resp @%d\n", tid, cycleCount)
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// Move on to a new operation
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currentOp := randOp
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// Operation finished
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opInProgress := UInt(0)
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}
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}
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// Delay
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when (currentOp === opDelay) {
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when (opInProgress === UInt(0)) {
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// Start timer
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delayTimer.io.start := Bool(true)
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// Multi-cycle operation now in progress
|
||||
opInProgress := UInt(1)
|
||||
}
|
||||
.elsewhen (delayTimer.io.timeout) {
|
||||
// Move on to a new operation
|
||||
currentOp := randOp
|
||||
// Operation finished
|
||||
opInProgress := UInt(0)
|
||||
}
|
||||
}
|
||||
|
||||
// Load, store, or atomic swap
|
||||
when (currentOp === opLoad ||
|
||||
currentOp === opStore ||
|
||||
currentOp === opSwap) {
|
||||
when (canSendFreshReq) {
|
||||
// Set address
|
||||
reqAddr := randAddr
|
||||
// Set command
|
||||
when (currentOp === opLoad) {
|
||||
reqCmd := M_XRD
|
||||
} .elsewhen (currentOp === opStore) {
|
||||
reqCmd := M_XWR
|
||||
} .elsewhen (currentOp === opSwap) {
|
||||
reqCmd := M_XA_SWAP
|
||||
}
|
||||
// Send request
|
||||
sendFreshReq := Bool(true)
|
||||
// Move on to a new operation
|
||||
currentOp := randOp
|
||||
}
|
||||
}
|
||||
|
||||
// Load-reserve and store-conditional
|
||||
// First issue an LR, then delay, then issue an SC
|
||||
when (currentOp === opLRSC) {
|
||||
// LR request has not yet been sent
|
||||
when (opInProgress === UInt(0)) {
|
||||
when (canSendFreshReq) {
|
||||
// Set address and command
|
||||
reqAddr := randAddr
|
||||
reqCmd := M_XLR
|
||||
// Send request
|
||||
sendFreshReq := Bool(true)
|
||||
// Multi-cycle operation now in progress
|
||||
opInProgress := UInt(1)
|
||||
}
|
||||
}
|
||||
// LR request has been sent, start delay timer
|
||||
when (opInProgress === UInt(1)) {
|
||||
// Start timer
|
||||
delayTimer.io.start := Bool(true)
|
||||
// Indicate that delay has started
|
||||
opInProgress := UInt(2)
|
||||
}
|
||||
// Delay in progress
|
||||
when (opInProgress === UInt(2)) {
|
||||
when (delayTimer.io.timeout) {
|
||||
// Delay finished
|
||||
opInProgress := UInt(3)
|
||||
}
|
||||
}
|
||||
// Delay finished, send SC request
|
||||
when (opInProgress === UInt(3)) {
|
||||
when (canSendFreshReq) {
|
||||
// Set command, but leave address
|
||||
// i.e. use same address as LR did
|
||||
reqCmd := M_XSC
|
||||
// Send request
|
||||
sendFreshReq := Bool(true)
|
||||
// Multi-cycle operation finished
|
||||
opInProgress := UInt(0)
|
||||
// Move on to a new operation
|
||||
currentOp := randOp
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Sending of requests
|
||||
// -------------------
|
||||
|
||||
when (sendFreshReq) {
|
||||
// Grab a unique tag for the request
|
||||
reqTag := Cat(UInt(0), tagMan.io.tagOut)
|
||||
tagMan.io.take := Bool(true)
|
||||
// Fill in unique data
|
||||
reqData := Cat(nextData, tid)
|
||||
nextData := nextData + UInt(1)
|
||||
// Request is good to go!
|
||||
reqValid := Bool(true)
|
||||
// Increment request count
|
||||
reqCount := reqCount + UInt(1)
|
||||
}
|
||||
.elsewhen (io.mem.req.fire()) {
|
||||
// Request has been sent and there is no new request ready
|
||||
reqValid := Bool(false)
|
||||
}
|
||||
|
||||
// Wire up interface to memory
|
||||
io.mem.req.valid := reqValid
|
||||
io.mem.req.bits.addr := reqAddr
|
||||
io.mem.req.bits.data := reqData
|
||||
io.mem.req.bits.typ := MT_D
|
||||
io.mem.req.bits.cmd := reqCmd
|
||||
io.mem.req.bits.tag := reqTag
|
||||
io.mem.req.bits.kill := Bool(false)
|
||||
io.mem.req.bits.phys := Bool(true)
|
||||
|
||||
// On cycle when request is actually sent, print it
|
||||
when (io.mem.req.fire()) {
|
||||
// Short-hand for address
|
||||
val addr = io.mem.req.bits.addr
|
||||
// Print thread id
|
||||
printf("%d:", tid)
|
||||
// Print command
|
||||
when (reqCmd === M_XRD) {
|
||||
printf(" load-req 0x%x", addr)
|
||||
}
|
||||
when (reqCmd === M_XLR) {
|
||||
printf(" load-reserve-req 0x%x", addr)
|
||||
}
|
||||
when (reqCmd === M_XWR) {
|
||||
printf(" store-req %d 0x%x", reqData, addr)
|
||||
}
|
||||
when (reqCmd === M_XSC) {
|
||||
printf(" store-cond-req %d 0x%x", reqData, addr)
|
||||
}
|
||||
when (reqCmd === M_XA_SWAP) {
|
||||
printf(" swap-req %d 0x%x", reqData, addr)
|
||||
}
|
||||
// Print tag
|
||||
printf(" #%d", reqTag)
|
||||
// Print time
|
||||
printf(" @%d\n", cycleCount)
|
||||
}
|
||||
|
||||
// Handling of responses
|
||||
// ---------------------
|
||||
|
||||
// When a response is received
|
||||
when (io.mem.resp.valid) {
|
||||
// Put tag back in tag set
|
||||
tagMan.io.tagIn := io.mem.resp.bits.tag
|
||||
tagMan.io.put := Bool(true)
|
||||
// Print response
|
||||
printf("%d: resp %d #%d @%d\n", tid,
|
||||
io.mem.resp.bits.data, io.mem.resp.bits.tag, cycleCount)
|
||||
// Increment response count
|
||||
respCount := respCount + UInt(1)
|
||||
}
|
||||
|
||||
// Response timeouts
|
||||
// -----------------
|
||||
//
|
||||
// Raise an error if a response takes too long to come back.
|
||||
|
||||
val timeout = Timer(memRespTimeout, io.mem.req.fire(), io.mem.resp.valid)
|
||||
assert(!timeout, s"Trace generator ${id} timed out waiting for response")
|
||||
|
||||
// Termination condition
|
||||
// ---------------------
|
||||
|
||||
io.finished := reqCount === UInt(numReqsPerGen) &&
|
||||
respCount === UInt(numReqsPerGen)
|
||||
}
|
||||
|
||||
// =======================
|
||||
// Trace-generator wrapper
|
||||
// =======================
|
||||
|
||||
class GroundTestTraceGenerator(id: Int)(implicit p: Parameters)
|
||||
extends GroundTest()(p) with HasTraceGenParams {
|
||||
|
||||
disablePorts(cache = false)
|
||||
|
||||
val traceGen = Module(new TraceGenerator(id))
|
||||
io.cache <> traceGen.io.mem
|
||||
|
||||
io.finished := traceGen.io.finished
|
||||
}
|
||||
|
|
@ -2,6 +2,12 @@ package groundtest
|
|||
|
||||
import Chisel._
|
||||
|
||||
// ============
|
||||
// Static timer
|
||||
// ============
|
||||
|
||||
// Timer with a statically-specified period.
|
||||
|
||||
class Timer(initCount: Int) extends Module {
|
||||
val io = new Bundle {
|
||||
val start = Bool(INPUT)
|
||||
|
|
@ -36,3 +42,112 @@ object Timer {
|
|||
timer.io.timeout
|
||||
}
|
||||
}
|
||||
|
||||
// =============
|
||||
// Dynamic timer
|
||||
// =============
|
||||
|
||||
// Timer with a dynamically-settable period.
|
||||
|
||||
class DynamicTimer(width: Int) extends Module {
|
||||
val io = new Bundle {
|
||||
val start = Bool(INPUT)
|
||||
val period = UInt(INPUT, width)
|
||||
val stop = Bool(INPUT)
|
||||
val timeout = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
val countdown = Reg(init = UInt(0, width))
|
||||
val active = Reg(init = Bool(false))
|
||||
|
||||
when (io.start) {
|
||||
countdown := io.period
|
||||
active := Bool(true)
|
||||
}
|
||||
.elsewhen (active) {
|
||||
countdown := countdown - UInt(1)
|
||||
}
|
||||
|
||||
when (io.stop) {
|
||||
active := Bool(false)
|
||||
}
|
||||
|
||||
io.timeout := countdown === UInt(0) && active
|
||||
}
|
||||
|
||||
// ============
|
||||
// LCG16 module
|
||||
// ============
|
||||
|
||||
// A 16-bit psuedo-random generator based on a linear conguential
|
||||
// generator (LCG). The state is stored in an unitialised register.
|
||||
// When using the C++ backend, it is straigtforward to arrange a
|
||||
// random initial value for each uninitialised register, effectively
|
||||
// seeding each LCG16 instance with a different seed.
|
||||
|
||||
class LCG16 extends Module {
|
||||
val io = new Bundle {
|
||||
val out = UInt(OUTPUT, 16)
|
||||
}
|
||||
val state = Reg(UInt(width = 32))
|
||||
state := state * UInt(1103515245, 32) + UInt(12345, 32)
|
||||
io.out := state(30, 15)
|
||||
}
|
||||
|
||||
// ==========
|
||||
// LCG module
|
||||
// ==========
|
||||
|
||||
// An n-bit psuedo-random generator made from many instances of a
|
||||
// 16-bit LCG. Parameter 'width' must be larger than 0.
|
||||
|
||||
class LCG(val width : Int) extends Module {
|
||||
val io = new Bundle {
|
||||
val out = UInt(OUTPUT, width)
|
||||
}
|
||||
require(width > 0)
|
||||
val numLCG16s : Int = (width+15)/16
|
||||
val outs = List.fill(numLCG16s)(Module(new LCG16()).io.out)
|
||||
io.out := Cat( outs(0)((width%16)-1, 0)
|
||||
, outs.drop(1) : _*)
|
||||
}
|
||||
|
||||
// ======================
|
||||
// Frequency distribution
|
||||
// ======================
|
||||
|
||||
// Given a list of (frequency, value) pairs, return a random value
|
||||
// according to the frequency distribution. The sum of the
|
||||
// frequencies in the distribution must be a power of two.
|
||||
|
||||
object Frequency {
|
||||
def apply(dist : List[(Int, Bits)]) : Bits = {
|
||||
// Distribution must be non-empty
|
||||
require(dist.length > 0)
|
||||
|
||||
// Require that the frequencies sum to a power of two
|
||||
val (freqs, vals) = dist.unzip
|
||||
val total = freqs.sum
|
||||
require(isPow2(total))
|
||||
|
||||
// First item in the distribution
|
||||
val (firstFreq, firstVal) = dist.head
|
||||
|
||||
// Result wire
|
||||
val result = Wire(Bits(width = firstVal.getWidth))
|
||||
result := UInt(0)
|
||||
|
||||
// Random value
|
||||
val randVal = Module(new LCG(log2Up(total))).io.out
|
||||
|
||||
// Pick return value
|
||||
var count = firstFreq
|
||||
var select = when (randVal < UInt(firstFreq)) { result := firstVal }
|
||||
for (p <- dist.drop(1)) {
|
||||
count = count + p._1
|
||||
select = select.elsewhen(randVal < UInt(count)) { result := p._2 }
|
||||
}
|
||||
|
||||
return result
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user