riscv/rocket-chip
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Don't assign SInt(-1) to a UInt

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Palmer Dabbelt 2016-03-14 16:53:55 -07:00 committed by Palmer Dabbelt
parent aa22f175c3
commit c9e1b72972
1 changed files with 1 additions and 1 deletions
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2
uncore/src/main/scala/cache.scala
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@ -953,7 +953,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
io.data.write.bits.way_en := xact_way_en
io.data.write.bits.addr_idx := xact_addr_idx
io.data.write.bits.addr_beat := curr_write_beat
io.data.write.bits.wmask := SInt(-1) // Always writes a full beat
io.data.write.bits.wmask := ~UInt(0, io.data.write.bits.wmask.getWidth)
io.data.write.bits.data := data_buffer(curr_write_beat)
// soon as the data is released, granted, put, or read from the cache