Merge pull request #54 from ucb-bar/fsim-no-htif
The FPGA doesn't have an HTIF clock divider
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0ac5c07683
@ -24,7 +24,11 @@ class htif_emulator_t : public htif_pthread_t
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void set_clock_divisor(int divisor, int hold_cycles)
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{
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#ifdef UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR
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/* We only want to write the HTIF clock divisor SCR on targets where it
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* actually exists (there isn't one on the FPGA, for example). */
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write_cr(-1, UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR, divisor | hold_cycles << 16);
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#endif
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}
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void start()
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