riscv/rocket-chip
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Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip

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This commit is contained in:
John Wright
2016-02-25 10:40:47 -08:00
committed by Palmer Dabbelt
parent 7fa38b5624
commit ba96ad2b38
2 changed files with 3 additions and 1 deletions
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src/main/scala/RocketChip.scala
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@@ -171,6 +171,8 @@ class Uncore(implicit val p: Parameters) extends Module
scrArb.io.in(0) <> htif.io.scr
scrArb.io.in(1) <> outmemsys.io.scr
scrFile.io.smi <> scrArb.io.out
scrFile.io.scr.attach(UInt(nTiles), "N_CORES", false, true)
scrFile.io.scr.attach(UInt(p(MMIOBase) >> 20), "MMIO_BASE", false, true)
// scrFile.io.scr <> (... your SCR connections ...)
// Configures the enabled memory channels. This can't be changed while the

2
uncore

Submodule uncore updated: 42549fd7cf...01e9a7f0ff