Merge pull request #55 from ucb-bar/travis-regression
travis-ci.org improvements
This commit is contained in:
Palmer Dabbelt
commit
700d756de0
66
.travis.yml
66
.travis.yml
@ -1,7 +1,12 @@
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language: scala
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# run on new infrastructure
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sudo: false
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cache: apt
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cache:
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apt: true
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directories:
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$HOME/.ivy2
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regression/install
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# packages needed to build riscv-tools
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addons:
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apt:
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@ -24,17 +29,14 @@ addons:
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- texinfo
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env:
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global:
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- RISCV="/home/travis/riscv_install"
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- PATH=$PATH:$RISCV/bin
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matrix:
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- VCONFIG=DefaultVLSIConfig FCONFIG=DefaultFPGAConfig ECONFIG=DefaultCPPConfig
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- VCONFIG=RoccExampleConfig FCONFIG=RoccExampleConfig ECONFIG=RoccExampleConfig
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- VCONFIG=DmaControllerConfig FCONFIG=DmaControllerFPGAConfig ECONFIG=DmaControllerConfig
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- VCONFIG=MemtestConfig FCONFIG=MemtestConfig ECONFIG=MemtestConfig
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- VCONFIG=MemtestL2Config FCONFIG=MemtestL2Config ECONFIG=MemtestL2Config
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- VCONFIG=BroadcastRegressionTestConfig FCONFIG=BroadcastRegressionTestConfig ECONFIG=BroadcastRegressionTestConfig
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- VCONFIG=CacheRegressionTestConfig FCONFIG=CacheRegressionTestConfig ECONFIG=CacheRegressionTestConfig
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- CONFIG=DefaultCPPConfig
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- CONFIG=RoccExampleConfig
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- CONFIG=DmaControllerConfig
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- CONFIG=MemtestConfig
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- CONFIG=MemtestL2Config
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- CONFIG=BroadcastRegressionTestConfig
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- CONFIG=CacheRegressionTestConfig
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# blacklist private branches
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branches:
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@ -44,41 +46,15 @@ branches:
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- hurricane
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before_install:
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# make install destination
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- mkdir -p $RISCV
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# don't do travis on riscv-tools
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- rm riscv-tools/.travis.yml
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# pull in needed repos from riscv-tools (travis isn't recursive)
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- cd riscv-tools
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- git submodule update --init riscv-fesvr
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- git submodule update --init riscv-gnu-toolchain
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- git submodule update --init riscv-tests
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- cd riscv-tests
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- git submodule update --init
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- cd ../..
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# use recently installed gcc
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- export CXX=g++-4.8 CC=gcc-4.8
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script:
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# test verilog
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- cd vsim
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- make CONFIG=$VCONFIG verilog
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- cd ../fsim
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- make CONFIG=$FCONFIG verilog
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# build riscv-fesvr
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- cd ../riscv-tools/riscv-fesvr
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- mkdir build
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- cd build
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- ../configure --prefix=$RISCV
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- make install
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# build emulator
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- cd ../../../emulator
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- make -j 8 CONFIG=$ECONFIG
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# build riscv-gcc
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- cd ../riscv-tools/riscv-gnu-toolchain
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- ./configure --prefix=$RISCV
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- make -j 8 > build.gcc.out
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# run riscv-tests
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- cd ../../emulator
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- make -j 8 CONFIG=$ECONFIG run-asm-tests
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- make CONFIG=$ECONFIG run-bmark-tests
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- make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
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- make fsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
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- make emulator-ndebug -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
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- make emulator-asm-tests -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
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- make emulator-bmark-tests -C regression CONFIG=$CONFIG TORTURE_CONFIG=default -j1
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before_cache:
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- ls -tr regression/install | tail -n+2 | sed s@^@regression/install/@ | xargs rm -rf
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@ -19,8 +19,12 @@ endif
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# The top-level directory that contains rocket-chip
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TOP ?= ..
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# The hash of the tools that we're using
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TOOLS_HASH ?= $(shell git -C $(TOP) ls-tree HEAD -- riscv-tools | xargs echo | cut -d' ' -f3)
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$(info Using riscv-tools of $(TOOLS_HASH))
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# The directory that the tools get built into.
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RISCV ?= install
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RISCV ?= install/$(TOOLS_HASH)
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# Torture saves the failing tests into a directory, which defaults to just somehing inside the regressions directory.
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TORTURE_SAVE_DIR ?= torture-failures
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@ -37,8 +41,8 @@ clean:
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# this order, since there's dependencies for everything it doesn't actually
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# matter. They're here to make running the various targets from the
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# commandline a bit cleaner.
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submodules: stamps/submodules.stamp
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tools: stamps/tools.stamp
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submodules: stamps/other-submodules.stamp
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tools: $(RISCV)/install.stamp
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emulator-debug: stamps/$(CONFIG)/emulator-debug.stamp
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emulator-ndebug: stamps/$(CONFIG)/emulator-ndebug.stamp
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@ -46,12 +50,14 @@ emulator-asm-tests: stamps/$(CONFIG)/emulator-asm-tests.stamp
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emulator-bmark-tests: stamps/$(CONFIG)/emulator-bmark-tests.stamp
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emulator-torture: stamps/$(CONFIG)/emulator-torture-$(TORTURE_CONFIG).stamp
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vsim-verilog: stamps/$(CONFIG)/vsim-verilog.stamp
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vsim-debug: stamps/$(CONFIG)/vsim-debug.stamp
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vsim-ndebug: stamps/$(CONFIG)/vsim-ndebug.stamp
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vsim-asm-tests: stamps/$(CONFIG)/vsim-asm-tests.stamp
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vsim-bmark-tests: stamps/$(CONFIG)/vsim-bmark-tests.stamp
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vsim-torture: stamps/$(CONFIG)/vsim-torture-$(TORTURE_CONFIG).stamp
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fsim-verilog: stamps/$(CONFIG)/fsim-verilog.stamp
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fsim-debug: stamps/$(CONFIG)/fsim-debug.stamp
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fsim-ndebug: stamps/$(CONFIG)/fsim-ndebug.stamp
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fsim-asm-tests: stamps/$(CONFIG)/fsim-asm-tests.stamp
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@ -59,47 +65,66 @@ fsim-bmark-tests: stamps/$(CONFIG)/fsim-bmark-tests.stamp
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fsim-torture: stamps/$(CONFIG)/fsim-torture-$(TORTURE_CONFIG).stamp
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# Checks out all the rocket-chip submodules
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stamps/submodules.stamp:
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stamps/other-submodules.stamp:
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mkdir -p $(dir $@)
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git -C $(abspath $(TOP)) submodule update --init --recursive
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touch $@
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git -C $(abspath $(TOP)) submodule update --init --recursive chisel
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git -C $(abspath $(TOP)) submodule update --init --recursive context-dependent-environments
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git -C $(abspath $(TOP)) submodule update --init --recursive dramsim2
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git -C $(abspath $(TOP)) submodule update --init --recursive groundtest
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git -C $(abspath $(TOP)) submodule update --init --recursive hardfloat
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git -C $(abspath $(TOP)) submodule update --init --recursive junctions
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git -C $(abspath $(TOP)) submodule update --init --recursive rocket
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git -C $(abspath $(TOP)) submodule update --init --recursive torture
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git -C $(abspath $(TOP)) submodule update --init --recursive uncore
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date > $@
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# Builds the RISC-V toolchain
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stamps/tools.stamp: stamps/submodules.stamp
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$(RISCV)/install.stamp:
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mkdir -p $(dir $@)
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git -C $(abspath $(TOP)) submodule update --init riscv-tools
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git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-gnu-toolchain
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git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-isa-sim
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git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-fesvr
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git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-opcodes
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git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-pk
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git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-tests
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+cd $(abspath $(TOP))/riscv-tools; RISCV=$(abspath $(RISCV)) ./build.sh
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touch $@
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date > $@
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# Builds the various simulators
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stamps/$(CONFIG)/%-ndebug.stamp: stamps/submodules.stamp stamps/tools.stamp
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stamps/$(CONFIG)/%-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-verilog.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) verilog
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date > $@
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stamps/$(CONFIG)/%-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-ndebug.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV))
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touch $@
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date > $@
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stamps/$(CONFIG)/%-debug.stamp: stamps/submodules.stamp stamps/tools.stamp
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stamps/$(CONFIG)/%-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-debug.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) debug
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touch $@
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date > $@
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# Runs tests on one of the simulators
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stamps/$(CONFIG)/%-asm-tests.stamp: stamps/$(CONFIG)/%-ndebug.stamp stamps/tools.stamp stamps/submodules.stamp
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stamps/$(CONFIG)/%-asm-tests.stamp: stamps/$(CONFIG)/%-ndebug.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-asm-tests.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) run-asm-tests
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touch $@
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date > $@
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stamps/$(CONFIG)/%-bmark-tests.stamp: stamps/$(CONFIG)/%-ndebug.stamp stamps/tools.stamp stamps/submodules.stamp
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stamps/$(CONFIG)/%-bmark-tests.stamp: stamps/$(CONFIG)/%-ndebug.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-bmark-tests.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) run-bmark-tests
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touch $@
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date > $@
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# The torture tests run subtly differently on the different targets, so they
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# don't have pattern rules like everything else does.
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stamps/$(CONFIG)/vsim-torture-$(TORTURE_CONFIG).stamp: stamps/$(CONFIG)/vsim-debug.stamp stamps/$(CONFIG)/vsim-ndebug.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/torture rnight RTL_CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) PATH="$(abspath $(RISCV)/bin:$(PATH))" OPTIONS="-C $(abspath $(TOP)/torture/config/$(TORTURE_CONFIG).config) -p $(abspath $(TORTURE_SAVE_DIR)) -m 30 -t 10"
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touch $@
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date > $@
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stamps/$(CONFIG)/emulator-torture-$(TORTURE_CONFIG).stamp: stamps/$(CONFIG)/emulator-debug.stamp stamps/$(CONFIG)/emulator-ndebug.stamp
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stamps/$(CONFIG)/emulator-torture-$(TORTURE_CONFIG).stamp: stamps/$(CONFIG)/emulator-debug.stamp stamps/$(CONFIG)/emulator-debug.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/torture cnight RTL_CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) PATH="$(abspath $(RISCV)/bin:$(PATH))" OPTIONS="-C $(abspath $(TOP)/torture/config/$(TORTURE_CONFIG).config) -p $(abspath $(TORTURE_SAVE_DIR)) -m 30 -t 10"
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touch $@
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date > $@
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@ -1 +1 @@
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Subproject commit 2065218d0a8c25ea721f8036d9098eb91a31920c
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Subproject commit 509c745061ce072e175015b9df83310a68eeb4a4
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@ -147,10 +147,10 @@ object DefaultTestSuites {
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val rv64u = List(rv64ui, rv64um, rv64ua)
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val rv64i = List(rv64ui, rv64si, rv64mi)
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val bmarks = new BenchmarkTestSuite("basic", "$(base_dir)/riscv-tools/riscv-tests/benchmarks", LinkedHashSet(
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val bmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
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"median", "multiply", "qsort", "towers", "vvadd", "mm", "dhrystone", "spmv", "mt-vvadd", "mt-matmul"))
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val mtBmarks = new BenchmarkTestSuite("mt", "$(base_dir)/riscv-tools/riscv-tests/mt",
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val mtBmarks = new BenchmarkTestSuite("mt", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/mt",
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LinkedHashSet(((0 to 4).map("vvadd"+_) ++
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List("ad","ae","af","ag","ai","ak","al","am","an","ap","aq","ar","at","av","ay","az",
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"bb","bc","bf","bh","bj","bk","bm","bo","br","bs","ce","cf","cg","ci","ck","cl",
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2
torture
2
torture
@ -1 +1 @@
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Subproject commit 733342509b271bffb3b6df51b85784abc6627ad8
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Subproject commit b54b3d0d80cd620ddcce1680201c6f366051d150
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