Updates to the trace-generator: (1) Don't terminate via HTIF exit, which can cause other, unfinished, cores to be cut short. Instead emit FINISHED messsages allowing an external process to send a SIGTERM to the emulator once all cores have finished. (2) Add some support for greater address variation without having to recompile, disabled by default. (3) Generate atomic, LR/SC, and fence operations by default in addition to plain loads and stores. These changes require newer versions of files in the rocket-chip/scripts directory. I will submit a pull request for those too.
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@ -45,25 +45,34 @@ import cde.{Parameters, Field}
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//
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// * The desired number of requests to be sent by each generator.
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//
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// * A list of physical addresses from which an address is drawn when
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// generating a fresh request.
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// * A bag of physical addresses, shared by all cores, from which an
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// address can be drawn when generating a fresh request.
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//
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// * A number of random 'extra addresses', local to each core, from
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// which an address can be drawn when generating a fresh request.
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// (This is a way to generate a wider range of addresses without having
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// to repeatedly recompile with a different address bag.)
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case object AddressBag extends Field[List[Int]]
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case object AddressBag extends Field[List[Int]]
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trait HasTraceGenParams {
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implicit val p: Parameters
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val numGens = p(NGenerators)
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val numBitsInId = log2Up(numGens)
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val numReqsPerGen = p(MaxGenerateRequests)
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val memRespTimeout = 4096
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val memRespTimeout = 1024
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val numBitsInWord = p(WordBits)
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val numBytesInWord = numBitsInWord / 8
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val numBitsInWordOffset = log2Up(numBytesInWord)
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val addressBag = p(AddressBag)
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val logNumAddrsInTrace = log2Up(addressBag.length)
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val addressBagLen = addressBag.length
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val logAddressBagLen = log2Up(addressBagLen)
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val genExtraAddrs = false
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val logNumExtraAddrs = 1
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val numExtraAddrs = 1 << logNumExtraAddrs
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require(numBytesInWord * 8 == numBitsInWord)
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require(1 << logNumAddrsInTrace == addressBag.length)
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require((1 << logAddressBagLen) == addressBagLen)
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}
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// ============
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@ -173,23 +182,50 @@ class TraceGenerator(id: Int)
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// Random addresses
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// ----------------
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// Address list taken from module parameters.
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val numAddrsInTrace = 1 << logNumAddrsInTrace
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// Address bag, shared by all cores, taken from module parameters.
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// In addition, there is a per-core random selection of extra addresses.
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val bagOfAddrs = addressBag.map(x => UInt(x, numBitsInWord))
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val extraAddrs = (0 to numExtraAddrs-1).
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map(i => Reg(UInt(width = 16)))
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// A random index into the address bag.
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val randAddrIndex = Module(new LCG(logNumAddrsInTrace)).io.out
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val randAddrBagIndex = Module(new LCG(logAddressBagLen)).io.out
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// A random address from the address bag.
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val addrIndices = (0 to numAddrsInTrace-1).
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map(i => UInt(i, logNumAddrsInTrace))
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val addrBagIndices = (0 to addressBagLen-1).
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map(i => UInt(i, logAddressBagLen))
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val randAddr = MuxLookup(randAddrIndex, UInt(0),
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addrIndices.zip(bagOfAddrs))
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val randAddrFromBag = MuxLookup(randAddrBagIndex, UInt(0),
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addrBagIndices.zip(bagOfAddrs))
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// Random address from the address bag or the extra addresses.
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val randAddr =
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if (! genExtraAddrs) {
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randAddrFromBag
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}
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else {
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// A random index into the extra addresses.
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val randExtraAddrIndex = Module(new LCG(logNumExtraAddrs)).io.out
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// A random address from the extra addresses.
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val extraAddrIndices = (0 to numExtraAddrs-1).
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map(i => UInt(i, logNumExtraAddrs))
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val randAddrFromExtra = Cat(UInt(0),
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MuxLookup(randExtraAddrIndex, UInt(0),
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extraAddrIndices.zip(extraAddrs)), UInt(0, 3))
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Frequency(List(
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(1, randAddrFromBag),
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(1, randAddrFromExtra)))
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}
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// Random opcodes
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// --------------
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@ -205,19 +241,12 @@ class TraceGenerator(id: Int)
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// Distribution specified as a list of (frequency,value) pairs.
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// NOTE: frequencies must sum to a power of two.
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//val randOp = Frequency(List(
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// (10, opLoad),
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// (10, opStore),
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// (4, opFence),
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// (3, opLRSC),
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// (3, opSwap),
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// (2, opDelay)))
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// For now, just generate loads and stores as this is enough to
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// expose strange behaviour.
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val randOp = Frequency(List(
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(15, opLoad),
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(15, opStore),
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(10, opLoad),
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(10, opStore),
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(4, opFence),
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(3, opLRSC),
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(3, opSwap),
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(2, opDelay)))
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// Request/response tags
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@ -319,7 +348,7 @@ class TraceGenerator(id: Int)
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opInProgress := UInt(1)
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}
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// Wait until all requests have had a response
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.elsewhen (io.mem.ordered && reqCount === respCount) {
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.elsewhen (reqCount === respCount) {
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// Emit fence response
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printf("%d: fence-resp @%d\n", tid, cycleCount)
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// Move on to a new operation
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@ -397,7 +426,8 @@ class TraceGenerator(id: Int)
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}
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}
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// Delay finished, send SC request
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when (opInProgress === UInt(3)) {
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//when (opInProgress === UInt(3)) {
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when (opInProgress === UInt(3) && !reqValid && reqCount === respCount) {
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when (canSendFreshReq) {
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// Set command, but leave address
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// i.e. use same address as LR did
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@ -487,18 +517,26 @@ class TraceGenerator(id: Int)
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}
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// Response timeouts
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// -----------------
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//
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// Raise an error if a response takes too long to come back.
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// ---------------------------
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val timeout = Timer(memRespTimeout, io.mem.req.fire(), io.mem.resp.valid)
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assert(!timeout, s"Trace generator ${id} timed out waiting for response")
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// Raise an error if a response takes too long to come back
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val timeout = Timer(memRespTimeout, sendFreshReq, io.mem.resp.valid)
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assert(!timeout, s"Core ${id}: response timeout")
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// Termination condition
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// ---------------------
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io.finished := reqCount === UInt(numReqsPerGen) &&
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respCount === UInt(numReqsPerGen)
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val done = reqCount === UInt(numReqsPerGen) &&
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respCount === UInt(numReqsPerGen)
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val donePulse = done && !Reg(init = Bool(false), next = done)
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// Emit that this thread has completed
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when (donePulse) {
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printf(s"FINISHED ${numGens}\n")
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}
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io.finished := Bool(false)
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}
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// =======================
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