index extraction bug
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@ -784,8 +784,8 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
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}
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// These IOs are used for routing in the parent
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val iacq_in_same_set = inSameSet(xact_addr_idx, io.iacq().addr_block)
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val irel_in_same_set = inSameSet(xact_addr_idx,io.irel().addr_block)
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val iacq_in_same_set = inSameSet(xact_addr_block, io.iacq().addr_block)
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val irel_in_same_set = inSameSet(xact_addr_block, io.irel().addr_block)
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val before_wb_alloc = Vec(s_meta_read, s_meta_resp, s_wb_req).contains(state)
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io.matches.iacq := (state =/= s_idle) && iacq_in_same_set
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io.matches.irel := (state =/= s_idle) &&
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