riscv/rocket-chip
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Make sure there's enough xact id bits

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Eric Love 2016-03-11 16:54:56 -08:00 committed by Howard Mao
parent 67e711844a
commit 8a47c3f346
1 changed files with 1 additions and 0 deletions
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uncore/src/main/scala/rtc.scala
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@ -51,6 +51,7 @@ class RTC(csr_MTIME: Int)(implicit p: Parameters) extends HtifModule
id = coreId,
addr = addrTable(coreId),
size = UInt(log2Up(csrDataBytes)))
require(p(MIFMasterTagBits) >= log2Up(nCores))
io.w.valid := sending_data
io.w.bits := NastiWriteDataChannel(data = rtc)