Fix MIF bug that cuts off upper xact id bits

2016-03-11 16:59:24 -08:00 · 2016-03-11 16:59:24 -08:00 · 4fc2a14a63
commit 4fc2a14a63
parent 9dc0cbdfa4
3 changed files with 8 additions and 3 deletions
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit aa67573876a6fdf9332dd7640439243213693d5d
+Subproject commit b0fa161f600cfa31f59bcae77b2fe7c97882b319
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@ -73,10 +73,15 @@ class DefaultConfig extends Config (
      case ASIdBits => 7
      case MIFTagBits => Dump("MIF_TAG_BITS",
                         // Bits needed at the L2 agent
-                         log2Up(site(NAcquireTransactors)+2) +
+                         site(MIFMasterTagBits) + 
                         // Bits added by NASTI interconnect
                         max(log2Up(site(MaxBanksPerMemoryChannel)),
                            (if (site(UseDma)) 3 else 2)))
+      case MIFMasterTagBits => log2Up(max(
+                                  site(NTiles),
+                                  max(
+                                    site(NAcquireTransactors)+2,
+                                    site(NDmaTransactors))))
      case MIFDataBits => Dump("MIF_DATA_BITS", 64)
      case MIFAddrBits => Dump("MIF_ADDR_BITS",
                               site(PAddrBits) - site(CacheBlockOffsetBits))
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit 2e2e297ee739902b63b8e04e3a7ad5a3ef87c28b
+Subproject commit 9d4a38e955a1ea8b2bd88dd599e3ffdebaf2b78c