riscv/rocket-chip
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fix some Chisel assertions

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This commit is contained in:
Howard Mao 2016-03-02 14:03:15 -08:00
parent 9c7e5bc6c0
commit 5e145515e1
2 changed files with 6 additions and 6 deletions
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2
rocket

@ -1 +1 @@
Subproject commit abda4649cf353a8dca1fdd2cc536cb015a6237b3
Subproject commit c79f2454abff77a043cca3124151f31f0b76e57f

10
src/main/scala/RocketChip.scala
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@ -272,7 +272,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val mmio_ic = Module(new NastiRecursiveInterconnect(nMasters, nSlaves, addrMap, mmioBase))
val channelConfigs = p(MemoryChannelMuxConfigs)
Predef.assert(channelConfigs.sortWith(_ > _)(0) == nMemChannels,
require(channelConfigs.sortWith(_ > _)(0) == nMemChannels,
"More memory channels elaborated than can be enabled")
val mem_ic =
if (channelConfigs.size == 1) {
@ -338,11 +338,11 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
mem_channels, io.mem, io.mem_backup, io.mem_backup_en,
1, htifW, p(CacheBlockOffsetBits))
for (i <- 1 until nMemChannels) { io.mem(i) <> mem_channels(i) }
assert(!Vec(mem_channels.map{ io => io.r.valid }).toBits.orR ||
!io.mem_backup_en ||
Vec(channelConfigs.map{i => UInt(i)})(io.memory_channel_mux_select) === UInt(1),
val mem_request = mem_channels.map(io => io.ar.valid || io.aw.valid).reduce(_ || _)
val config_nchannels = Vec(channelConfigs.map(i => UInt(i)))(io.memory_channel_mux_select)
assert(!mem_request || !io.mem_backup_en || config_nchannels === UInt(1),
"Backup memory port only works when 1 memory channel is enabled")
Predef.assert(channelConfigs.sortWith(_ < _)(0) == 1,
require(channelConfigs.sortWith(_ < _)(0) == 1,
"Backup memory port requires a single memory port mux config")
} else { io.mem <> mem_channels }
}