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Avoid generating 0-width UInts

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Chisel3 requires a 1-bit width to represent UInt(0).
This commit is contained in:
Palmer Dabbelt 2016-03-06 16:32:14 -08:00 committed by Henry Cook
parent 2eafc4c8f3
commit 8c7e29eacd
1 changed files with 4 additions and 1 deletions
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5
uncore/src/main/scala/cache.scala
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@ -1116,7 +1116,10 @@ class L2WritebackUnit(trackerId: Int)(implicit p: Parameters) extends L2XactTrac
val xact_vol_irel_src = Reg{ io.irel().client_id }
val xact_vol_irel_client_xact_id = Reg{ io.irel().client_xact_id }
val xact_addr_block = Cat(xact.tag, xact.idx, UInt(cacheId, cacheIdBits))
val xact_addr_block = if (cacheIdBits == 0)
Cat(xact.tag, xact.idx)
else
Cat(xact.tag, xact.idx, UInt(cacheId, cacheIdBits))
val xact_vol_irel = Release(
src = xact_vol_irel_src,
voluntary = Bool(true),