riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Commit Graph

  • c38dff0855 add some more warnings about the StatelessBridge Howard Mao 2016-07-21 15:07:10 -0700
  • c31c650def If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge. Megan Wachs 2016-07-18 14:12:22 -0700
  • eb9e998c08 Add ManagerToClientStatelessBridge Megan Wachs 2016-07-18 13:09:44 -0700
  • 0a1cd64786 fix number of builtin Acquire types Howard Mao 2016-07-21 13:45:20 -0700
  • ffe17cbb2b bump uncore for L2 bugfix Howard Mao 2016-07-21 12:35:38 -0700
  • 20df74d138 generate more L1 voluntary releases in TraceGen Howard Mao 2016-07-20 11:06:47 -0700
  • 86e31be820 fix lockup from back to back releases with data Howard Mao 2016-07-20 18:23:27 -0700
  • 24ef4e6dea make sure to use AND not OR for combining finished signals Howard Mao 2016-07-21 12:05:11 -0700
  • d77d0ddc5d rename CacheTest.scala to CacheFillTest.scala Howard Mao 2016-07-20 20:37:45 -0700
  • d56362f04c add configuration checks for TraceGen Howard Mao 2016-07-20 10:37:10 -0700
  • 959630630a give LCG an inc signal and add object constructors Howard Mao 2016-07-20 09:41:45 -0700
  • b013925ab0 make sure ReleaseRegression starts only on io.start Howard Mao 2016-07-19 15:42:45 -0700
  • 9ae23f18bd rocket: support asynchronous external busses Wesley W. Terpstra 2016-07-18 14:09:10 -0700
  • fa8317fec1 debug: add clock crossing primitives Wesley W. Terpstra 2016-07-18 14:29:13 -0700
  • 577c73667b use getSimpleName to dump out test names Howard Mao 2016-07-19 14:42:58 -0700
  • 1dac2930eb fix bug in WriteMaskedPutBlockRegression Howard Mao 2016-07-19 14:42:23 -0700
  • 19b44ec95b Bug fixes in SimpleHellaCacheIF and L2 agents Howard Mao 2016-07-19 09:32:52 -0700
  • bc39d52655 changes to multi-transaction timer Howard Mao 2016-07-18 18:26:18 -0700
  • e406d1bd73 Make probeCopy have same behavior as probeDowngrade Henry Cook 2016-07-18 18:22:49 -0700
  • c069e66056 Modify the RoCC interface to include status in the command queue. (#41) Ben Keller 2016-07-18 17:40:50 -0700
  • 9eeb1112d4 fix Bufferless irel_vs_iacq_conflict signal Howard Mao 2016-07-18 17:38:20 -0700
  • e5cccc0526 don't update xact_vol_irel if not a voluntary irel Howard Mao 2016-07-18 17:05:23 -0700
  • 2723b2f515 fix issues in SimpleHellaCacheIF and document the changes Howard Mao 2016-07-18 17:02:47 -0700
  • 40a146f625 HellaCacheArbiter passes through if n == 1 Howard Mao 2016-07-18 17:01:29 -0700
  • 39a1ecbf3c switch groundtest to merged master Howard Mao 2016-07-18 09:34:27 -0700
  • 359252fdc1 fix a width bug Howard Mao 2016-07-15 18:46:20 -0700
  • 6fc4236782 add atomic and prefetch drivers Howard Mao 2016-07-15 16:37:33 -0700
  • 2ec736ed67 reorder some code in the Nasti unit tests Howard Mao 2016-07-15 15:41:15 -0700
  • 3ea299b062 make unit test debug output more meaningful Howard Mao 2016-07-15 15:40:11 -0700
  • def740406c fix a few Driver bugs Howard Mao 2016-07-15 15:39:46 -0700
  • 8278a73e83 group unit tests by their tested interface Howard Mao 2016-07-15 14:20:50 -0700
  • 9c0fffdd1c start constructing composable tilelink unit test drivers Howard Mao 2016-07-15 11:14:15 -0700
  • c92732dcaa rename MemoryTestDriver to NastiDriver Howard Mao 2016-07-15 11:08:02 -0700
  • c906e6edde some renaming Howard Mao 2016-07-14 13:41:59 -0700
  • 1c2bf6e938 make list of unit tests a a parameter Howard Mao 2016-07-14 12:28:20 -0700
  • 69eebaf362 factor out unit tests into separate package Howard Mao 2016-07-14 12:18:11 -0700
  • 4af6313288 TraceGen: Lookup -> MuxLookup Matthew Naylor 2016-07-17 22:28:18 +0100
  • e08ec42bc0 refactor groundtest unittests into separate package Howard Mao 2016-07-14 12:19:10 -0700
  • 59d700bf66 fix combinational loop in NASTI -> HASTI converter Howard Mao 2016-07-15 18:45:37 -0700
  • cff8de9814 Use new Mul/Div parameters vs UseFastMulDiv (#48) mwachs5 2016-07-15 15:41:20 -0700
  • 407bc95c42 Rename MulDivUnroll to MulUnroll Megan Wachs 2016-07-15 15:40:17 -0700
  • 897e6ccf8a fix Hasti and Smi converters Howard Mao 2016-07-15 15:39:00 -0700
  • 4c26a6bc96 Create seperate Mul/Div paramters instead of UseFastMulDiv Megan Wachs 2016-07-15 14:40:37 -0700
  • 84098db81f add a TileLinkTestRAM Howard Mao 2016-07-15 11:03:26 -0700
  • 7cf44f9b25 clean up WideCounter implementation Andrew Waterman 2016-07-15 00:51:01 -0700
  • ba08255450 bump rocket Andrew Waterman 2016-07-14 22:11:19 -0700
  • d78f1aacd0 Clean up some zero-width wire cases using UInt.extract Andrew Waterman 2016-07-14 21:42:12 -0700
  • da512d4230 Explicitly discard BTB index LSBs Andrew Waterman 2016-07-14 17:10:27 -0700
  • 768403f8fa Bump rocket; remove ICacheBufferWays parameter Andrew Waterman 2016-07-14 12:47:41 -0700
  • e6aab368a4 Replace ICacheBufferWays parameter with I$ constructor argument Andrew Waterman 2016-07-14 12:38:54 -0700
  • 3d0b92afd7 Misc code cleanup Andrew Waterman 2016-07-14 12:09:34 -0700
  • b8884e8143 Simplify frontend virtual address extension code Andrew Waterman 2016-07-14 12:05:09 -0700
  • 66b9c5ad05 fix up cloneType calls in clock crossers Howard Mao 2016-07-13 14:31:19 -0700
  • eeae74e3fc nasti: include convenient clock crossing helpers Wesley W. Terpstra 2016-07-12 19:41:40 -0700
  • c33c0944be crossing: first clock crossing, the handshaker Wesley W. Terpstra 2016-07-12 19:41:10 -0700
  • 18ea58c85f remove unnecessary CAMs from converters Howard Mao 2016-07-13 11:35:32 -0700
  • b122a54c32 don't allow more outer IDs than inner IDs Howard Mao 2016-07-13 12:42:28 -0700
  • 37fd11870c fix up ReorderQueue CAM Howard Mao 2016-07-13 12:11:43 -0700
  • de1e25f3d1 reduce usage of CAMs in converters Howard Mao 2016-07-13 11:08:36 -0700
  • c0dc09b3a1 don't use CAM in ReorderQueue if not necessary Howard Mao 2016-07-13 11:08:15 -0700
  • f3775df04d fix the condition under which comparator error signal is set Howard Mao 2016-07-12 17:12:22 -0700
  • 4c79215fde add a script for checking comparator trace Howard Mao 2016-07-12 11:10:43 -0700
  • 88dc0b983a make sure Comparator logs correctly when prefetching off Howard Mao 2016-07-12 14:36:46 -0700
  • 676a536706 fix bugs from adding ComparatorSource backpressure Howard Mao 2016-07-12 13:47:42 -0700
  • d435bb4185 reduce hardware usage of Comparator to allow it to synthesize Howard Mao 2016-07-12 10:54:18 -0700
  • 2f70136f90 Fix the Nasti to Smi Converter for single-word Nasti busses Palmer Dabbelt 2016-06-15 21:54:59 -0700
  • 90bcd3dbdc make sure DirectGroundTest testers given correct TL settings Howard Mao 2016-07-11 17:50:56 -0700
  • 8f0fa11ce4 optionally export detailed status information in DirectGroundTest Howard Mao 2016-07-11 12:17:29 -0700
  • b64998ec05 make sure dramsim reads and writes occur in the order they are received Howard Mao 2016-07-11 12:16:24 -0700
  • cb2a18b533 allow direct instatiation of arbitrary non-caching groundtests Howard Mao 2016-07-11 12:10:27 -0700
  • f03ffb32a0 add top that directly tests the TL -> AXI converters Howard Mao 2016-07-08 17:56:28 -0700
  • b47f8fbc41 don't use splat and bug out if too many address map entries Howard Mao 2016-07-11 18:10:42 -0700
  • 18967642de export more detailed status data from GroundTest Howard Mao 2016-07-11 16:41:55 -0700
  • 46fc9744e2 rocket: add an AXI master port into the chip Wesley W. Terpstra 2016-07-05 12:43:33 -0700
  • 8ac7fa5544 ext: support multiple external AHB/AXI ports Wesley W. Terpstra 2016-07-05 12:40:14 -0700
  • e194677087 fix comparator PutBlock data generation and debug output Howard Mao 2016-07-11 12:15:37 -0700
  • 36720d915a Update README.md (#161) mwachs5 2016-07-11 00:34:13 -0700
  • 9751ea0f35 Fix Verilator VCD (#157) Andrew Waterman 2016-07-09 02:37:39 -0700
  • 1699622730 Don't speculatively refill I$ in uncacheable regions Andrew Waterman 2016-07-09 01:08:52 -0700
  • 5a3d6a1583 NastiTest should cycle through write ids Howard Mao 2016-07-08 17:55:02 -0700
  • 9ec55ebb91 don't add io:ext region to address map if no external MMIO Howard Mao 2016-07-08 15:29:35 -0700
  • 35547aa428 allow NastiConverterTest and Memtest to run simultaneously Howard Mao 2016-07-08 13:40:52 -0700
  • d80c2f480f make NastiConverterTest act as generator and share blocks Howard Mao 2016-07-08 13:39:46 -0700
  • 358668699f refactoring groundtest configuration Howard Mao 2016-07-08 11:40:16 -0700
  • 850fa092a4 refactor how groundtests are configured Howard Mao 2016-07-08 11:40:01 -0700
  • eeac405ef8 get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache Howard Mao 2016-07-07 19:01:27 -0700
  • 8aa73915a1 put locking arbiter back into converter Howard Mao 2016-07-07 18:57:38 -0700
  • a50ba39ea7 Revert "add buffering and locking to TL -> Nasti converter" Howard Mao 2016-07-07 18:54:02 -0700
  • 32ee5432dd Fix testing of DefaultSmallConfig; bump rocket et al Andrew Waterman 2016-07-07 19:34:03 -0700
  • 70b677ecda Vec considered harmful; use isOneOf instead (#64) Andrew Waterman 2016-07-07 19:25:57 -0700
  • f7b392306e make sure SimpleHellaCacheIF can work with blocking DCache Howard Mao 2016-07-07 18:51:23 -0700
  • f62c74b82a allow groundtest to use non-blocking DCache Howard Mao 2016-07-07 18:59:09 -0700
  • 3d8939d3c3 Set misa.base = 1 for RV32 Andrew Waterman 2016-07-07 15:30:23 -0700
  • 2455a806af Make WFI instruction respect mie CSR setting Andrew Waterman 2016-07-07 15:30:43 -0700
  • 67871654dd start NastiConverterTest higher up in memory Howard Mao 2016-07-07 14:35:04 -0700
  • 16a6b11081 fix bug in AXI -> TL converter Howard Mao 2016-07-07 14:34:24 -0700
  • 7cc64011fb simplify amo_mask generation Howard Mao 2016-07-07 12:14:45 -0700
  • 1c5e7be75b make sure Nasti write channel id is set correctly Howard Mao 2016-07-07 12:14:02 -0700
  • 6055482513 make sure write channel id is actually set Howard Mao 2016-07-07 12:12:39 -0700
  • 8ccc50a8f0 fix IdMapper and TL -> NASTI converter Howard Mao 2016-07-07 10:16:44 -0700