Andrew Waterman
3b0c1ed0c3
Cope with changes to AddrMap
2016-06-03 13:50:29 -07:00
Andrew Waterman
cf8be98b2b
Cope with changes to AddrMap
2016-06-03 13:48:43 -07:00
Andrew Waterman
2e88ffc364
Cope with changes to AddrMap
2016-06-03 13:48:09 -07:00
Andrew Waterman
28161cab45
Merge AddrHashMap and AddrMap
2016-06-03 13:46:53 -07:00
Andrew Waterman
f1745bf142
Allow PLIC nPriorities=0 (priority fixed at 1)
2016-06-02 13:48:29 -07:00
Andrew Waterman
b7ca2145b3
Fix PLIC control bug when !grant.ready
2016-06-02 13:47:59 -07:00
Andrew Waterman
c8338ad809
Instantiate Debug Module ( #119 )
2016-06-02 10:53:41 -07:00
Andrew Waterman
0866b4c045
Can't assign to Vec literals
2016-06-01 23:36:34 -07:00
Andrew Waterman
20e1de08da
Avoid chisel2 pitfall
...
This code is erroneously flagged as incompatible with chisel3.
In fact, it is correct in both chisel2 and chisel3. D'oh.
2016-06-01 23:35:49 -07:00
Andrew Waterman
5629fb62bf
Avoid bitwise sub-assignment
2016-06-01 21:59:02 -07:00
Andrew Waterman
9518b3d589
Fix arithmetic in ROM row count
2016-06-01 21:59:02 -07:00
Andrew Waterman
8e80d1ec80
Avoid floating-point arithmetic where integers suffice
2016-06-01 21:59:02 -07:00
Andrew Waterman
13386af1d1
Get rid of unused implicit conversion
2016-06-01 19:30:41 -07:00
Andrew Waterman
9949347569
First stab at debug interrupts
2016-06-01 16:57:10 -07:00
Wesley W. Terpstra
11b3cee07a
Ahb tweaks ( #50 )
...
* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully
I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.
* ahb: optionally disable atomics => optimize to nothing
Trust the compiler the compiler to optimize away unused logic.
2016-06-01 16:42:39 -07:00
Wesley W. Terpstra
695be2f0ae
hasti: work-around unsupported 0-width signals
2016-06-01 16:38:49 -07:00
mwachs5
740a6073f6
Add Debug Module ( #49 )
...
* Add Debug Module
* [debug] Remove unit tests, update System Bus register addresses, parameterize nComponents
* [debug] Update Debug ROM contents to match updated addresses
2016-06-01 16:33:33 -07:00
Howard Mao
8983b0e865
hopefully the last fix for AXI -> AHB converter
2016-06-01 15:01:52 -07:00
Howard Mao
a917f554fd
use Wesley's test SRAM for AXI -> AHB converter test
2016-06-01 11:40:59 -07:00
Howard Mao
53a0e6cb9c
another fix for AXI -> AHB converter
2016-06-01 11:35:36 -07:00
Howard Mao
e8408f0a8a
fix HastiRAM
2016-06-01 10:33:59 -07:00
Howard Mao
d0988902f2
fix NASTI -> HASTI bridge
2016-05-31 19:47:50 -07:00
Howard Mao
8f269b2eec
stall for more cycles in Hasti test
2016-05-31 19:46:42 -07:00
Andrew Waterman
1311e78d3f
Add blocking D$ flush support
2016-05-31 19:28:41 -07:00
Andrew Waterman
51379621d6
Flush blocking D$ on FENCE.I
2016-05-31 19:27:28 -07:00
Andrew Waterman
6d82c0d156
Add M_FLUSH_ALL command
2016-05-31 19:25:31 -07:00
Howard Mao
50e3caef36
get rid of Zscale file I missed last time
2016-05-31 14:33:38 -07:00
Andrew Waterman
44a216038f
Use more generic TileLinkWidthAdapter
2016-05-27 13:38:13 -07:00
Andrew Waterman
56897f707a
Don't rely on Mux1H output when no inputs are hot
2016-05-27 13:38:01 -07:00
Andrew Waterman
3ee5144923
Fix TLB tag check logic when ASIDs are present
2016-05-27 12:24:17 -07:00
Andrew Waterman
056d7ec93a
Drive hmastlock low in Nasti-Hasti converter
2016-05-27 12:23:18 -07:00
Matthew Naylor
2a7e7172a9
Update docs for the trace generator
2016-05-27 10:54:35 +01:00
Andrew Waterman
8afdd7e3da
Work around PutBlocks draining into data array prematurely
2016-05-26 23:08:05 -07:00
Andrew Waterman
c104b57c52
Use BitPat implicit conversion in instruction decoder
2016-05-26 22:23:21 -07:00
Andrew Waterman
96fa1eb6ad
Add UInt->BitPat implicit conversion
...
This will be removed from Chisel3, so we're putting it here to maintain
compatibility.
2016-05-26 18:52:53 -07:00
Andrew Waterman
10f0e13c25
Use more parsimonious queue depths
2016-05-26 18:04:22 -07:00
Andrew Waterman
3cc236e9c4
By default, use same TileLink width everywhere
...
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
2016-05-26 18:04:01 -07:00
Andrew Waterman
391a9b9110
Use buses, rather than crossbars, by default in TLInterconnect
...
We should eventually parameterize this, of course.
2016-05-26 16:10:42 -07:00
Andrew Waterman
75f06d6e84
Use generic TileLink width adapter
2016-05-26 16:00:17 -07:00
Andrew Waterman
b6d26e90f8
Add generic TileLink width adapter
2016-05-26 15:59:42 -07:00
Andrew Waterman
e036d3a04a
Chisel3: gender issue
2016-05-26 15:59:08 -07:00
Andrew Waterman
8139f71dfb
Work around Chisel2 bug
...
This code is correct, but Chisel2 erroneously flags it as a Chisel3
compatibility error because it looks like Vec(Reg) when factor=1.
2016-05-26 12:37:31 -07:00
Matthew Naylor
b734beec06
Update build instructions
...
The emulator now requires an ELF file even when running ground tests.
(The ELF contains the tohost and fromhost addresses for communication
with the FESVR.)
2016-05-26 14:42:26 +01:00
Andrew Waterman
a2b9d337b6
No need for full-throughput queues in NastiErrorSlave
2016-05-26 01:03:40 -07:00
Andrew Waterman
2ece3e6102
Use Mem for ReorderQueue data
...
This might improve FPGA QoR.
2016-05-26 01:02:56 -07:00
Andrew Waterman
ddfa30e215
Work around zero-width wire limitations
2016-05-26 00:48:54 -07:00
Andrew Waterman
0c50bfcfb3
Work around more zero-width wire cases
2016-05-25 21:47:48 -07:00
Andrew Waterman
22568de5f3
Work around another zero-width wire limitation
2016-05-25 21:42:02 -07:00
Andrew Waterman
e2755a0f0a
Work around zero-width wire limitation in HTIF
2016-05-25 20:39:53 -07:00
Andrew Waterman
3e238adc67
rtc: fix acquire message type check
2016-05-25 20:37:48 -07:00